Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

1 . A semiconductor memory device comprising:
 a plurality of memory cells arranged in multiple column groups, each column group having,
 a plurality of columns, 
 a plurality of external bit-lines for independent multi-way configurable access, 
 a first, second and third level of hierarchy in the external bit-lines, wherein the first level of the hierarchy provides connectivity to the plurality of memory cells, the second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line, and the third level of the hierarchy including a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. 
   
     
     
         2 . The device of  claim 1  wherein each of the memory cells include,
 a metal-insulator-metal capacitor connected to a gate of an isolation transistor,   a transistor for writing connected to an input bit line; and   a transistor for reading connected to an output bit line.   
     
     
         3 . The memory cell in  claim 1 , wherein the plurality of memory cells are configured for metal programming to one of a hard logic zero or a one at time of manufacture. 
     
     
         4 . The memory cell of  claim 1 , wherein the memory cell is included in a multi-chip module package. 
     
     
         5 . A method for designing a circuit device and a layout in a manner to enhance yield of the circuit device during manufacturing, comprising:
 partitioning a physical design of the circuit device into different hierarchical levels of integration; and   providing a pool of redundant features for the different hierarchical levels of integration, wherein the pool of redundant features is apportioned to the different hierarchical levels of integration according to a defect density of each of the levels of integration.   
     
     
         6 . The method of  claim 5 , wherein providing a pool of redundant features includes,
 associating a greater amount of redundant features to lower hierarchical levels of integration; and   applying defect resilient techniques to higher hierarchical levels of integration in order to reduce an amount of redundant features associated with the higher hierarchical levels of integration.   
     
     
         7 . The method of  claim 6  wherein the defect resilient techniques include spacing features further apart. 
     
     
         8 . The method of  claim 5 , wherein the circuit device includes a multiple level array of memory storage cells. 
     
     
         9 . The method of  claim 6  wherein the lower hierarchical levels of integration include a transistor level of integration and the higher levels of integration include a page level of integration. 
     
     
         10 . A method to enhance soft error robustness of a semiconductor circuit device having a multiple level array of memory storage cells, comprising;
 isolating a read access path coupled to a memory storage cell of the multiple level array of memory storage cells;   increasing a charge of the memory storage cell that is in addition to a gate capacitance provided by a gate of the memory storage cell, and   reducing a diffusion area of a gate region of the memory storage cell, thereby reducing a soft error rate (SER) cross section.   
     
     
         11 . The method of  claim 10 , further comprising:
 performing single bit soft error detection and correction.   
     
     
         12 . A method for configuring and programming a semiconductor circuit device having a multiple level array of memory storage cells, comprising:
 expressing a stateful transaction oriented application as a network of FlowVirtualMachines (FVMs), each of the FVMs associated with a portion of a configurable memory region;   aggregating multiple FVMs into an AggregateFlowVirtualMachine (AFVM);   mapping the AFVM into a portion of the multiple level array of memory storage cells;   configuring multi-way access paths of the multiple level array according to the multiple FVMs; and   programming the portion of the multiple level array to function according to the multiple FVMs.   
     
     
         13 . The method of  claim 12 , wherein multiple AFVMs are mapped into a FlowTile. 
     
     
         14 . The method of  claim 13 , wherein a FlowTile is a physical entity that has a number of memory resource units and wherein a sum of resources required by the multiple AFVMs is less than the number of memory resources.