Stacked microelectronic layer and module with three-axis channel t-connects

Abstract

A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted leads terminate at the edge. Channels are formed in a surface of the module or on the surface of a layer whereby the rerouted leads are disposed within the channel. The entire surface of the edge or layer is metalized and a predetermined portion of the metalization removed such that the rerouted leads within each channel are electrically connected to each other.

1 . A method comprising:
 assembling a stack including at least two layers, wherein each layer comprises an integrated circuit and a conductive trace configured to electrically connect a contact pad of the layer to an access lead at an edge of the layer, and wherein the edges of the layers are aligned to define a planar surface of the stack;   forming a channel in the planar surface of the stack to expose the access leads of the at least two layers; and   providing a conductive material in the channel to electrically connect the access leads of the at least two layers.   
     
     
         2 . The method of  claim 1 , wherein each integrated circuit comprises a wire ball bond electrically connected to the contact pad. 
     
     
         3 . The method of  claim 1 , wherein at least one of the layers comprises a prepackaged microelectronic circuit. 
     
     
         4 . The method of  claim 1 , wherein at least one of the layers comprises a thin small-outline package. 
     
     
         5 . The method of  claim 1 , wherein at least one of the layers comprises a modified thin small-outline package. 
     
     
         6 . The method of  claim 1 , wherein at least one of the layers comprises a ball grid array package electrically connected to an interposer layer. 
     
     
         7 . The method of  claim 1 , wherein at least one of the layers comprises a neolayer that includes at least one integrated circuit die encapsulated in a dielectric material, and wherein the neolayer further includes at least one metal conductor disposed on a surface of the neolayer and configured to route electronic signals of the integrated circuit die to the access leads. 
     
     
         8 . The method of  claim 1 , wherein said providing a conductive material in the channel comprises depositing the conductive material over the entire planar surface and into the channel and removing excess conductive material from the planar surface. 
     
     
         9 . The method of  claim 1 , wherein said forming a channel comprises at least one of saw-cutting, routering, or milling the planar surface. 
     
     
         10 . The method of  claim 1 , wherein said providing a conductive material in the channel comprises sputtering the conductive material into the channel. 
     
     
         11 . The method of  claim 1 , wherein at least a portion of the access leads of the at least two layers are aligned. 
     
     
         12 . The method of  claim 1 , wherein at least one of the access leads is wider than the channel. 
     
     
         13 . The method of  claim 1 , further comprising electrically connecting the access leads to the conductive material using a T-connect structure. 
     
     
         14 . The method of  claim 1 , wherein the channel has a non-linear geometry. 
     
     
         15 . A method comprising:
 forming a channel in a planar surface of a stack having at least two layers to expose at least one access lead for each of the at least two layers, wherein each layer includes an integrated circuit and a conductive trace configured to electrically connect a contact pad of the layer to an access lead located at an edge of the layer; and   depositing a conductive material in the channel to electrically connect the exposed access leads;   wherein the at least two layers are aligned such that edges of the layers define the planar surface.   
     
     
         16 . The method of  claim 15 , wherein each integrated circuit is electrically connected to the contact pad via a wire ball bond. 
     
     
         17 . The method of  claim 15 , wherein at least one of the layers comprises a prepackaged microelectronic circuit, a thin small-outline package, a modified thin small-outline package, or a ball grid array package electrically connected to an interposer layer. 
     
     
         18 . The method of  claim 15 , wherein at least one of the layers comprises a neolayer that includes at least one integrated circuit die encapsulated in a dielectric material, and wherein the neolayer further includes at least one metal electrically connecting the integrated circuit die to the access leads. 
     
     
         19 . The method of  claim 15 , wherein said depositing a conductive material in the channel comprises depositing the conductive material over the entire planar surface and into the channel and removing excess conductive material from the planar surface. 
     
     
         20 . The method of  claim 15 , wherein said forming a channel in a planar surface comprises at least one of saw-cutting, routering, or milling the planar surface. 
     
     
         21 . The method of  claim 15 , wherein said depositing a conductive material in the channel comprises sputtering the conductive material into the channel. 
     
     
         22 . The method of  claim 15 , wherein at least a portion of each of the exposed access leads are aligned. 
     
     
         23 . The method of  claim 15 , wherein at least one of the exposed access leads is wider than the channel. 
     
     
         24 . The method of  claim 15 , further comprising forming a T-connect structure to electrically connect the access leads to the conductive material in the channel. 
     
     
         25 . A method comprising:
 forming a stack by coupling a first layer having a first integrated circuit to a second layer having a second integrated circuit; and   electrically connecting a first access lead of the first layer to a second access lead of the second layer by forming a channel in a surface of the stack to expose the first and second access leads and introducing a conductive material into the channel;   wherein the first access lead is electrically connected to the first integrated circuit and the second access lead is electrically connected to the second integrated circuit.   
     
     
         26 . The method of  claim 25 , wherein at least one of the first or second integrated circuits is electrically connected to the respective first or second access lead via a contact pad. 
     
     
         27 . The method of  claim 25 , wherein at least one of the first or second layers comprises a prepackaged microelectronic circuit, a thin small-outline package, a modified thin small-outline package, or a ball grid array package electrically connected to an interposer layer. 
     
     
         28 . The method of  claim 25 , wherein at least one of the first or second layers comprises a neolayer that includes at least one integrated circuit die encapsulated in a dielectric material and a metal electrically connecting the integrated circuit die to at least one of the first or second access leads. 
     
     
         29 . The method of  claim 25 , wherein said introducing a conductive material into the channel comprises depositing the conductive material over the surface of the stack and into the channel and removing conductive material from the surface. 
     
     
         30 . The method of  claim 25 , wherein said forming a channel in a surface of the stack comprises at least one of saw-cutting, routering, or milling a planar surface of the stack. 
     
     
         31 . The method of  claim 25 , wherein said introducing a conductive material into the channel comprises sputtering the conductive material into the channel. 
     
     
         32 . The method of  claim 25 , wherein at least a portion of the first and second access leads are aligned. 
     
     
         33 . The method of  claim 25 , wherein a width of at least one of the first or second access leads is greater than a width of the channel. 
     
     
         34 . The method of  claim 25 , further comprising electrically connecting the first and second access leads to the conductive material using a T-connect structure.