Structured semiconductor element for reducing charging effects

Abstract

A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect structures are connected to semiconductor circuit elements arranged downstream.

1 - 12 . (canceled) 
   
   
       13 . A method for reducing undesirable charging effects, comprising:
 electrically insulating interconnect structures on a surface of a semiconductor circuit element from the remainder of the surface of the semiconductor circuit element; and   exclusively connecting the interconnect structures to semiconductor circuit elements arranged downstream.   
   
   
       14 . The method of  claim 13 , further comprising configuring the circuit element as a connection element of test structures for semiconductor circuits. 
   
   
       15 . The method of  claim 14 , where a permissible area free of interconnect structures on the surface of the semiconductor circuit element is smaller than an expected minimum contact area of a contact needle. 
   
   
       16 . The method of  claim 14 , further comprising forming the semiconductor circuit element as a connection pad for test structures. 
   
   
       17 . The method of  claim 14 , further comprising forming the semiconductor circuit element as a protective structure for charge-sensitive layers. 
   
   
       18 . A method for forming a semiconductor circuit element that reduces undesirable charging effects, the method comprising:
 providing a surface for the semiconductor circuit element;   forming interconnect structures in a portion of the semiconductor circuit element, the portion of the surface of semiconductor circuit element having interconnect structures being electrically insulated from the remainder of the surface of the semiconductor circuit element; and   exclusively connecting the interconnect structures to semiconductor circuit elements arranged downstream.   
   
   
       19 . The method of  claim 18 , where the circuit element comprises a connection element of test structures for semiconductor circuits. 
   
   
       20 . The method of  claim 19 , further comprising providing a permissible area free of interconnect structures on the surface of the semiconductor circuit element being smaller than an expected minimum contact area of a contact needle. 
   
   
       21 . The method of  claim 20 , where the semiconductor circuit element comprises a connection pad for test structures. 
   
   
       22 . The method of  claim 21 , where the semiconductor circuit element comprises a protective structure for charge-sensitive layers. 
   
   
       23 . A semiconductor element, comprising:
 means for electrically insulating interconnect structures on a surface of a semiconductor circuit element from the remainder of the surface of the semiconductor circuit element; and   means for exclusively connecting the interconnect structures to semiconductor circuit elements arranged downstream.   
   
   
       24 - 25 . (canceled)