Link transmitter with reduced power consumption

Abstract

With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.

1 . A chip, comprising:
 a transmitter circuit to generate a differential signal and communicate it to a receiver, the transmitter to operate in an active mode where the differential signal has an associated common mode level and signal difference and in a low power mode where the signal has an associated common mode level that is less than the active mode common mode level and a signal difference sufficient to be perceived by the receiver.   
   
   
       2 . The chip of  claim 1 , in which the transmitter comprises drivers selectably and additively coupled to one another to generate the differential signal. 
   
   
       3 . The chip of  claim 2 , in which at least some of the drivers are gated off during the low power mode. 
   
   
       4 . The chip of  claim 3 , in which the drivers are differently weighted, the largest weighted driver remaining on to produce a signal difference when the transmitter is in the low power mode. 
   
   
       5 . The chip of  claim 4 , in which the drivers are binary weighted. 
   
   
       6 . The chip of  claim 2 , in which the transmitter comprises a bias generator to bias the generators at different levels during the active and low power modes. 
   
   
       7 . The chip of  claim 6 , in which the receiver includes an error detection circuit to enable the drivers to be biased at a reduced level, using an initial training sequence, while in the active mode. 
   
   
       8 . The chip of  claim 1 , in which the transmitter can also operate in an idle mode having an associated common mode level that is close to the active mode common mode level and a signal difference approaching zero. 
   
   
       9 . A chip, comprising:
 a transmitter circuit to generate a differential signal and communicate it to a receiver, the transmitter to operate in an active mode where the differential signal has an associated common mode level and signal difference and in a low power mode where the signal has an associated common mode level that is less than the active mode common mode level and a signal difference sufficient to be perceived by the receiver, the transmitter comprising drivers selectably and additively coupled to one another to generate the differential signal.   
   
   
       10 . The chip of  claim 9 , in which at least some of the drivers are gated off during the low power mode. 
   
   
       11 . The chip of  claim 10 , in which the drivers are differently weighted, the largest weighted driver remaining on to produce a signal difference when the transmitter is in the low power mode. 
   
   
       12 . The chip of  claim 11 , in which the drivers are binary weighted. 
   
   
       13 . The chip of  claim 9 , in which the transmitter comprises a bias generator to bias the generators at different levels during the active and low power modes. 
   
   
       14 . The chip of  claim 13 , in which the receiver includes an error detection circuit to enable the drivers to be biased at a reduced level, using an initial training sequence, while in the active mode. 
   
   
       15 . The chip of  claim 9 , in which the transmitter can also operate in an idle mode having an associated common mode level that is close to the active mode common mode level and a signal difference approaching zero. 
   
   
       16 . A computer comprising:
 a microprocessor chip having a transmitter circuit;   a wireless interface chip having a receiver to be linked to the microprocessor chip transmitter, the transmitter to generate a differential signal and communicate it to the receiver, the transmitter to operate in an active mode where the differential signal has an associated common mode level and signal difference and in a low power mode where the signal has an associated common mode level that is less than the active mode common mode level and a signal difference sufficient to be perceived by the receiver; and   an antenna coupled to the wireless interface chip to electromagnetically link it to a wireless network.   
   
   
       17 . The computer of  claim 16 , in which the transmitter comprises drivers selectably and additively coupled to one another to generate the differential signal. 
   
   
       18 . The computer of  claim 17 , in which at least some of the drivers are gated off during the low power mode. 
   
   
       19 . The computer of  claim 18 , in which the drivers are differently weighted, the largest weighted driver remaining on to produce a signal difference when the transmitter is in the low power mode. 
   
   
       20 . The computer of  claim 19 , in which the drivers are binary weighted. 
   
   
       21 . The computer of  claim 17 , in which the transmitter comprises a bias generator to bias the generators at different levels during the active and low power modes.