Current sample and hold circuit and method and demultiplexer and display device using the same

Abstract

A data current sample and hold circuit having an input terminal of a current source type and an output terminal of a current sink type. The sample and hold circuit includes a first transistor, a capacitor, and a plurality of switches, for sampling and holding the data current sunk to an output terminal of a data driver. When the sampled and held data current is applied to the data line, the data current is sunk to an output terminal of the sample and hold circuit. The sample and hold circuit is used together with a data driver having an output terminal of the current sink type.

1 . A current demultiplexer comprising: at least one sample and hold circuit group, each said sample and hold circuit group including a predetermined number of sample and hold circuits, and having an input terminal and an output terminal,
 wherein input terminals of the sample and hold circuit groups are coupled to each other,   wherein input terminals of the sample and hold circuits are coupled to each other, and output terminals of the sample and hold circuits are coupled to each other in each said sample and hold circuit group, and they sequentially sample and hold a current, and   wherein the sample and hold circuits arranged in the same order of the respective sample and hold circuit groups sequentially sample and hold the current with each other.   
   
   
       2 . The current demultiplexer of  claim 1 , wherein each said sample and hold circuit comprises:
 a first transistor;   a first switch coupled to the first transistor so that the first transistor can be diode-connected in response to a first control signal applied to the first switch;   a capacitor coupled to the first transistor so that a source-gate voltage of the first transistor can be charged in the capacitor in response to the first control signal;   a second switch for inputting the data to a drain of the first transistor in response to the first control signal; and   a third switch for outputting the data from a source of the first transistor in response to a second control signal using the source-gate voltage charged in the capacitor.   
   
   
       3 . The current demultiplexer of  claim 2 , wherein each said sample and hold circuit further comprises:
 a fourth switch for coupling the source of the first transistor to a first power source in response to a third control signal; and   a fifth switch for coupling the drain of the first transistor to a second power source in response to a fourth control signal.   
   
   
       4 . The current demultiplexer of  claim 1 , wherein the current demultiplexer includes N groups for performing a 1:N demultiplexing function, and wherein output terminals of the sample and hold circuit groups are independent of each other. 
   
   
       5 . A display device comprising:
 a data current driver for providing a data current;   a plurality of sample and hold circuits, each said sample and hold circuit coupled to an output terminal of the data current driver, for sampling and holding the data current;   a data line coupled to an output terminal of one of the sample and hold circuits; and   a pixel circuit coupled to the data line, wherein a current sink format or a current source format of an input terminal and an output terminal of said one of the sample and hold circuits are different.   
   
   
       6 . The display device of  claim 5 , wherein each said sample and hold circuit comprises:
 a first transistor;   a first switch coupled to the first transistor so that the first transistor can be diode-connected in response to a first control signal applied to the first switch;   a capacitor coupled to the first transistor so that a source-gate voltage of the first transistor can be charged in the capacitor in response to the first control signal;   a second switch for inputting the data to a drain of the first transistor in response to the first control signal; and   a third switch for outputting the data from a source of the first transistor in response to a second control signal using the source-gate voltage charged in the capacitor.   
   
   
       7 . The display device of  claim 6 , wherein each said sample and hold circuit further comprises:
 a fourth switch for coupling the source of the first transistor to a first power source in response to a third control signal; and   a fifth switch for coupling the drain of the first transistor to a second power source in response to a fourth control signal.   
   
   
       8 . The display device of  claim 5 , wherein the data current driver includes an output terminal having the current sink format, and the pixel circuit includes an input terminal having the current source format. 
   
   
       9 . A display device comprising:
 a data current driver for providing a data current;   a demultiplexer, coupled to an output terminal of the data current driver, for demultiplexing the data current;   a data line coupled to an output terminal of the demultiplexer; and   a pixel circuit coupled to the data line,   wherein the demultiplexer comprises at least one sample and hold circuit group, each said sample and hold circuit group including a predetermined number of sample and hold circuits and having an input terminal and an output terminal,   wherein input terminals of the sample and hold circuit groups are coupled to each other,   wherein input terminals of the sample and hold circuits are coupled to each other, and output terminals of the sample and hold circuits are coupled to each other in each group, and they sequentially sample and hold the data current, and   wherein the sample and hold circuits arranged in the same order of the respective sample and hold circuit groups sequentially sample and hold the data current with each other.   
   
   
       10 . The display device of  claim 9 , wherein each said sample and hold circuit comprises:
 a first transistor;   a first switch coupled to the first transistor so that the first transistor can be diode-connected in response to a first control signal applied to the first switch;   a capacitor coupled to the first transistor so that a source-gate voltage of the first transistor can be charged in the capacitor in response to the first control signal;   a second switch for inputting the data to a drain of the first transistor in response to the first control signal; and   a third switch for outputting the data from a source of the first transistor in response to a second control signal using the source-gate voltage charged in the capacitor.   
   
   
       11 . The display device of  claim 10 , wherein the sample and hold circuit further comprises:
 a fourth switch for coupling the source of the first transistor to a first power source in response to a third control signal; and   a fifth switch for coupling the drain of the first transistor to a second power source in response to a fourth control signal.