Panel Driving Circuit that Generates Panel Test Pattern and Panel Test Method Thereof

Abstract

A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

1 . A panel driving circuit comprising:
 a pattern generation unit that produces first pattern test data and first pattern test signals in response to a system clock; and   a selection unit that chooses and outputs one of (a) the first pattern test data and the first pattern test signals that are outputted from the pattern generation unit, and (b) second pattern test data and second pattern test signals that are applied directly from outside of the pattern generation unit.   
   
   
       2 . The panel driving circuit of  claim 1 , wherein the first pattern test data comprises data for testing an external panel, and wherein the first pattern test signals comprises a horizontal synchronizing signal, a vertical synchronizing signal, and a data activating signal with which the pattern test data is synchronized. 
   
   
       3 . The panel driving circuit of  claim 2 , wherein the pattern generation unit comprises:
 a first counter that calculates and outputs the number of cycles of the system clock;   a horizontal synchronizing signal generation unit that receives the output of the first counter and produces the horizontal synchronizing signal whenever the output of the first counter reaches a predetermined value;   a data activating signal generation unit that receives the output of the first counter and produces the data activating signal whenever the output of the first counter reaches a predetermined value;   a second counter that calculates the number of cycles of the horizontal synchronizing signals;   a vertical synchronizing signal that receives the output of the second counter and produces the vertical synchronizing signal whenever the output of the second counter reaches a predetermined value;   a third counter that calculates the number of cycles of the vertical synchronizing signals;   a pattern decision making unit that responds to the output of the third counter and produces a pattern signal that decides which test pattern will examine the panel; and   a data storage unit that (a) responds to the output of the second counter and the pattern signal, and (b) outputs the first pattern test data.   
   
   
       4 . The panel driving circuit of  claim 3 , wherein the predetermined value of the horizontal and the vertical synchronizing signal generation units are decided by the size of the panel. 
   
   
       5 . The panel driving circuit of  claim 3 , wherein the data activating signal is activated during the cycle of the horizontal synchronizing signal except for a certain amount of time after the horizontal synchronizing signal is produced and before the next cycle of the horizontal synchronizing signal is to be produced. 
   
   
       6 . The panel driving circuit of  claim 3 , wherein the pattern decision making unit comprises a plurality of the test patterns for examining the panel. 
   
   
       7 . The panel driving circuit of  claim 1 , further comprising a control unit that (a) receives the pattern test data, the pattern test signals, and the system clock, which are outputted from the selection unit, and (b) applies the pattern test data, the pattern test signals, and the system clock to the external panel. 
   
   
       8 . A method of testing a panel, wherein a driving circuit generates pattern test data and pattern test signals to test the panel, the method comprising:
 determining whether a test signal is activated or not activated;   if the test signal is activated, in response to a system clock, generating first pattern test data and first pattern test signals and applying the first pattern test data and the first pattern test signals to the panel; and   if the test signal is not activated, applying second pattern test data and second pattern test signals that are directly applied from the outside to the panel.   
   
   
       9 . The method of  claim 8 , wherein the first pattern test data tests an external panel, and the first pattern test signals comprise a horizontal synchronizing signal, a vertical synchronizing signal, and a data activating signal with which the pattern test data is synchronized. 
   
   
       10 . The method of  claim 9 , wherein generating the pattern test data and the pattern test signals comprises:
 calculating the number of cycles of the system clock;   generating the horizontal synchronizing signal whenever the number of cycles of the system clock that is calculated reaches a predetermined value;   generating the data activating signal whenever the number of cycles of the system clock reaches a predetermined value;   calculating the number of cycles of the horizontal synchronizing signal;   generating a vertical synchronizing signal whenever the number of cycles of the horizontal synchronizing signal reaches a predetermined value;   calculating the number of cycles of the vertical synchronizing signal;   in response to the vertical synchronizing signal, generating a pattern signal that decides which test pattern will check the panel; and   in response to the number of cycles of the horizontal synchronizing signal and the pattern signal, outputting the first pattern test data.   
   
   
       11 . The method of  claim 10 , wherein the predetermined value to generate the horizontal synchronizing signal and the vertical synchronizing signal is decided based on the size of the panel. 
   
   
       12 . The method of  claim 10 , wherein the data activating signal is activated during the cycle of the horizontal synchronizing signal except for a certain amount of time after the horizontal synchronizing signal is produced and before the next cycle of the horizontal synchronizing signal is to be produced. 
   
   
       13 . A system of testing a panel, wherein a driving circuit generates pattern test data and pattern test signals to test the panel, the method comprising:
 means for determining whether a test signal is activated or not activated;   if the test signal is activated, in response to a system clock, means for generating first pattern test data and first pattern test signals and applying the first pattern test data and the first pattern test signals to the panel; and   if the test signal is not activated, means for applying second pattern test data and second pattern test signals that are directly applied from the outside to the panel.   
   
   
       14 . The system of  claim 13 , wherein means for generating the pattern test data and the pattern test signals comprises:
 means for calculating the number of cycles of the system clock;   means for generating the horizontal synchronizing signal whenever the number of cycles of the system clock that is calculated reaches a predetermined value;   means for generating the data activating signal whenever the number of cycles of the system clock reaches a predetermined value;   means for calculating the number of cycles of the horizontal synchronizing signal;   means for generating a vertical synchronizing signal whenever the number of cycles of the horizontal synchronizing signal reaches a predetermined value;   means for calculating the number of cycles of the vertical synchronizing signal;   in response to the vertical synchronizing signal, means for generating a pattern signal that decides which test pattern will check the panel; and   in response to the number of cycles of the horizontal synchronizing signal and the pattern signal, means for outputting the first pattern test data.