Cmos imager and apparatus with selectively silicided gates

Abstract

The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

1 - 86 . (canceled) 
   
   
       87 . An apparatus, comprising:
 a pixel array, each pixel of the array comprising at least one silicided transistor gate, at least one transistor source/drain that is not silicided, and at least one photosensor that is not silicided to prevent light blockage;   a readout circuit configured to provide correlated sampling of each pixel of the array; and   an analog-to-digital converter coupled to receive signals from pixels of the array.   
   
   
       88 . The apparatus of  claim 87 , wherein each pixel of the array further comprises a plurality of silicided transistor gates. 
   
   
       89 . The apparatus of  claim 88 , wherein the silicided transistor gates include a refractory metal. 
   
   
       90 . The apparatus of  claim 89 , wherein the silicided transistor gates further include a barrier metal layer. 
   
   
       91 . The apparatus of  claim 87 , wherein the at least one silicided transistor gate further includes a barrier metal layer. 
   
   
       92 . The apparatus of  claim 87 , wherein the at least one photosensor is a photogate. 
   
   
       93 . The apparatus of  claim 87 , further comprising image processing circuitry for processing signals-derived from the pixel array. 
   
   
       94 . The apparatus of  claim 87 , wherein the at least one silicided transistor gate is a transfer transistor gate. 
   
   
       95 . The apparatus of  claim 87 , wherein the at least one silicided transistor gate is a reset transistor gate. 
   
   
       96 . The apparatus of  claim 87 , wherein the apparatus is a CMOS imager. 
   
   
       97 . The apparatus of  claim 96 , further comprising a plurality of photosensors that are not silicided and a plurality of reset transistors each having a silicided reset gate, each reset transistor capable of resetting a corresponding one of the photosensors, wherein regions above the photosensors and above the sources and drains of the reset transistors are not silicided. 
   
   
       98 . The apparatus of  claim 97 , wherein the pixel array further comprises a plurality of transfer transistors each having a silicided transfer gate, each transfer transistor capable of transferring charges from a corresponding one of the photosensors, wherein the regions above the sources and drains of the transfer transistors are not silicided. 
   
   
       99 . The apparatus of  claim 98 , wherein the pixel array further comprises a plurality of row select and source follower transistors coupled in series, wherein each row select and source follower transistor has a silicided gate. 
   
   
       100 . The apparatus of  claim 98 , wherein the silicided reset gates and the silicided transfer gates further comprise a barrier metal layer. 
   
   
       101 . The apparatus of  claim 97 , wherein the silicided reset gates further include a barrier metal layer. 
   
   
       102 . The apparatus of  claim 97 , wherein the photosensors are photogates. 
   
   
       103 . The apparatus of  claim 97 , further comprising image processing circuitry for processing signals derived from the pixel array. 
   
   
       104 . The apparatus of  claim 103 , further comprising a plurality of load transistors and source follower transistors coupled in series, wherein each source follower transistor has a silicided gate. 
   
   
       105 . The apparatus of  claim 97 , further comprising a plurality of load transistors and source follower transistors coupled in series, wherein each source follower transistor has a silicided gate.