Flat Panel Display

Abstract

A display includes an array of pixel circuits and data drivers to drive the pixel circuits. The data drivers include a first data driver to receive pixel data according to a first clock frequency and to forward some of the pixel data to a second data driver according to a second clock frequency, the second clock frequency being different from the first clock frequency.

1 . A display, comprising:
 an array of pixel circuits; and   data drivers to drive the pixel circuits, the data drivers comprising a first data driver to receive pixel data, the first data driver using a first portion of the pixel data to drive a first portion of the pixel circuits, the first data driver forwarding a second portion of the pixel data to a second data driver and a third portion of the pixel data to a third data driver, the second portion of the pixel data being sent to the second data driver without passing through the third data driver, the third portion of the pixel data being sent to the third data driver without passing through the second data driver.   
     
     
         2 . The display of  claim 1  in which the first data driver sends different portions of the pixel data to the second data driver and a third data driver alternately during alternate clock cycles. 
     
     
         3 . The display of  claim 1 , further comprising transmission lines disposed on a glass substrate to transmit pixel data from the first data driver to the second data driver. 
     
     
         4 . The display of  claim 1  in which the first data driver comprises a transistor-transistor-logic (TTL) interface to send the pixel data to the second data driver. 
     
     
         5 . The display of  claim 1  in which the first data driver comprises a differential signaling interface to send the pixel data to the second data driver. 
     
     
         6 . The display of  claim 1  in which the second data driver comprises a first transistor-transistor-logic (TTL) interface and a second TTL interface, the first TTL interface to receive portions of the pixel data from the first data driver, the second TTL interface to forward portions of the pixel data to a third data driver. 
     
     
         7 . The display of  claim 1 , further comprising a timing controller to output a first clock signal having pulses, a second clock signal having pulses that correspond to odd number pulses of the first clock signal, and a third clock signal having pulses that correspond to even number pulses of the first clock signal. 
     
     
         8 . The display of  claim 7  in which the first data driver sends some of the pixel data to the second data driver according to the second clock signal, and sends some of the pixel data to the third data driver according to the third clock signal. 
     
     
         9 . The display of  claim 8  in which the second clock frequency is lower than the first clock frequency. 
     
     
         10 . The display of  claim 1  in which the first, second, and third data drivers are disposed outside the array of pixel circuits and near an edge of a glass substrate of the display, the first data driver being positioned between the second and third data drivers. 
     
     
         11 . A display, comprising:
 an array of pixel circuits;   a first data driver to receive first pixel data from a timing controller and use the first pixel data to drive a first portion of the pixel circuits, wherein the first data driver also receives second pixel data and third pixel data from the timing controller, the second and third pixel data not used by the first data driver in driving pixel circuits;   a second data driver to receive the second pixel data from the first data driver and use the second pixel data to drive a second portion of the pixel circuits; and   a third data driver to receive the third pixel data from the first data driver and use the third pixel data to drive a third portion of the pixel circuits, the third pixel data not passing the second data driver, the second pixel data not passing the third data driver.   
     
     
         12 . The display of  claim 11  wherein the first data driver sends the additional pixel data to the second data driver through signal lines attached to a glass substrate of the display. 
     
     
         13 . The display of  claim 11  wherein the first data driver receives the additional pixel data from the timing controller according to a first clock frequency, and the first data driver sends the additional pixel data to the second data driver according to a second clock frequency that is different from the first clock frequency. 
     
     
         14 . The display of  claim 11  in which the first data driver comprises a transistor-transistor-logic (TTL) interface to send the additional pixel data to the second data driver. 
     
     
         15 . The display of  claim 11  in which the first data driver comprises a differential signaling interface to send the additional pixel data to the second data driver. 
     
     
         16 . The display of  claim 11  in which the first, second, and third data drivers are disposed outside the array of pixel circuits and near an edge of a glass substrate of the display, the first data driver being positioned between the second and third data drivers. 
     
     
         17 . A display, comprising:
 a substrate;   an array of pixel circuits disposed on the substrate;   a timing controller to output pixel data, a first clock signal, a second clock signal, and a third clock signal, each of the second and third clock signals having a frequency that is less than the frequency of the first clock signal;   a first data driver to drive corresponding pixel circuits;   a second data driver to drive corresponding pixel circuits; and   a third data driver to drive corresponding pixel circuits, in which
 during a first time period, the first data driver receives pixel data from the timing controller according to the first clock signal and stores the pixel data in a buffer, and 
 during a second time period, the first data driver receives pixel data from the timing controller according to the first clock signal, sends some of the pixel data to the second data driver according to the second clock signal, and sends some of the pixel data to the third data driver according to the third clock signal, each of the second and third data drivers storing the received pixel data in a buffer, the pixel data sent to the second data driver not passing through the third data driver, the pixel data sent to the third data driver not passing through the second data driver. 
   
     
     
         18 . The display of  claim 17  in which the first, second, and third data drivers are disposed outside the array of pixel circuits and near an edge of a glass substrate of the display, the first data driver being positioned between the second and third data drivers. 
     
     
         19 . A method of operating a display, comprising:
 transmitting pixel data from a timing controller to a first data driver at a first clock frequency; and   transmitting the pixel data from the first data driver to a second data driver at a second clock frequency without passing the pixel data through a third data driver, the second clock frequency being different from the first clock frequency; and   transmitting the pixel data from the first data driver to the third data driver at a third clock frequency without passing the pixel data through the second data driver, the third clock frequency being different from the first clock frequency.   
     
     
         20 . The method of  claim 19 , further comprising driving pixel circuits using the second data driver based on the pixel data received at the second data driver. 
     
     
         21 . The method of  claim 19 , comprising disposing the first, second, and third data drivers outside an active display area and near an edge of a glass substrate of the display, and positioning the first data driver between the second and third data drivers 
     
     
         22 . A method of operating a display that comprises an array of pixel circuits, the method comprising:
 transmitting first pixel data from a timing controller to a first data driver;   transmitting second pixel data from the timing controller to the first data driver;   transmitting the second pixel data from the first data driver to a second data driver without passing the second pixel data through a third data driver;   transmitting third pixel data from the timing controller to the first data driver; and   transmitting the third pixel data from the first data driver to the third data driver without passing the third pixel data through the second data driver.   
     
     
         23 . The method of  claim 22  wherein transmitting the second pixel data from the first data driver to the second data driver comprises transmitting the second pixel data from the first data driver to the second data driver through signal lines attached to a glass substrate. 
     
     
         24 . The method of  claim 22  wherein the first pixel data has information about chroma values for a first portion of a row of pixel circuits, and the second pixel data has information about chroma values for a second portion of the row of pixel circuits. 
     
     
         25 . The method of  claim 22 , comprising disposing the first, second, and third data drivers outside the array of pixel circuits and near an edge of a glass substrate of the display, and positioning the first data driver between the second and third data drivers.