Clock reproducing apparatus

Abstract

A clock reproducing apparatus includes a clock reproducing circuit having: a gated oscillator having an oscillating circuit of two routes; and a frequency control circuit for comparing a phase of an output of the gated oscillator with a phase of a reference clock, and supplying a phase control signal to the gated oscillator based on the comparison result so as to set a delay time, input data is input to a reset input terminal of the gated oscillator, and different route of the two routes of the oscillating circuit operates depending on a case where the input data is “H” and a case where the input data is “L”.

1 . A clock reproducing apparatus comprising:
 a clock reproducing circuit,   wherein the clock reproducing circuit includes:
 an oscillator, which is synchronized with the alternation timing of input data and switches two routes; and 
 a frequency control circuit for comparing a phase of an output of the oscillator with a phase of a reference clock, and supplying a phase control signal to the oscillator based on the comparison result so as to set a delay time, 
   wherein input data is input to a reset input terminal of the oscillator,   characterized in that   the oscillator comprises at least two delay units, wherein each of the delay units is connected to the reset input terminal of the oscillator, and wherein   each delay unit comprises two routes being alternately activated depending on the input data, and wherein the input data are either “H” or “L”.   
   
   
       2 . The clock reproducing apparatus as claimed in  claim 1 , characterized in that when one of the two routes of the oscillating circuit of the oscillator operates, the other of the two routes of the oscillating circuit on a non-operating side is reset. 
   
   
       3 . A clock reproducing apparatus comprising:
 a pulse forming circuit which receives input data and forms a pulse from the input data; and   a clock reproducing circuit,   wherein the clock reproducing circuit includes:
 an oscillator, which is synchronized with the alternation timing of input data and switches two routes; and 
 a frequency control circuit for comparing a phase of an output of the oscillator with a phase of a reference clock, and supplying a phase control signal to the oscillator based on the comparison result so as to set a delay time, and 
   wherein an output of the pulse forming circuit resets the oscillator, and   wherein an output of the oscillator is provided as a clock reproducing output,   characterized in that
 the oscillator comprises at least two delay units, wherein each of the delay units is connected to a reset input terminal of the oscillator, and wherein 
   each delay unit comprises two routes being alternately activated depending on the input data, and wherein the input data are either “H” or “L”.   
   
   
       4 . The clock reproducing apparatus as claimed in  claim 3 , characterized in that the pulse forming circuit is a differentiating circuit for differentiating the input data. 
   
   
       5 . The clock reproducing apparatus as claimed in  claim 3 , characterized in that the pulse forming circuit includes an AND gate for providing an AND of the input data and a signal that is obtained by delaying the input data for a predetermined amount. 
   
   
       6 . The clock reproducing apparatus as claimed in  claim 3 , characterized in that the pulse forming circuit includes an exclusive OR gate for providing an exclusive OR of the input data and a signal that is obtained by delaying the input data for a predetermined amount. 
   
   
       7 . A clock reproducing apparatus comprising:
 a pulse forming circuit which detects a head of a packet which is input data and forms a reset pulse that is synchronized with the detected head; and   a clock reproducing circuit,   wherein the clock reproducing circuit includes:   an oscillator, which is synchronized with the alternation timing of input data and switches two routes; and   a frequency control circuit for comparing a phase of an output of the oscillator with a phase of a reference clock, and supplying a phase control signal to the oscillator based on the comparison result so as to set a delay time, and   wherein an output of the pulse forming circuit resets the oscillator, and   wherein an output of the oscillator is provided as a clock reproducing output,   
     characterized in that
 the oscillator comprises at least two delay units, wherein each of the delay units is connected to a reset input terminal of the oscillator, and wherein 
 each delay unit comprises two routes being alternately activated depending on the input data, and wherein the input data are either “H” or “L”. 
 
   
   
       8 . The clock reproducing apparatus as claimed in  claim 1 , wherein serial input data is provided to the reset input terminal as the “H” data or the “L” data to alternately switch the routes. 
   
   
       9 . The clock reproducing apparatus as claimed in  claim 1 , wherein a first of said two routes becomes active on the basis of timing when the serial data is switching from “L” to “H” and the clock is generated which is synchronized with switching timing from “L” to “H” of the serial data, and wherein a second of said two routes becomes active on the basis of timing when the serial data is switched for “H” to “L” and the clock is generated which is synchronized with switching timing from “H” to “L” of the serial data. 
   
   
       10 . The clock reproducing apparatus as claimed in  claim 1 , wherein the oscillator continues oscillation and a phase of the clock which is generated from the oscillator at the switching timing of “H” to “L” or “L” to “H” of the serial data is aligned. 
   
   
       11 . The clock reproducing apparatus as claimed in  claim 1 , wherein when a first route of the two routes is selected, a second route of the two routes is reset such that activation of the two routes is mutually exclusive.