Method and device for improving clock stability

Abstract

A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock.. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.

1 . A method for improving clock stability, comprising:
 determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value;   pre-processing the ST and the RT, if the difference between the ST and RT is a mutated value;   acquiring a service clock according to the pre-processed ST and RT; and   sending time division multiplex (TDM) data according to the service clock.   
   
   
       2 . The method of  claim 1 , further comprising:
 receiving packet data, recording the current RT, and separating TDM data and the ST from the packet data.   
   
   
       3 . The method of  claim 2 , wherein the separating TDM data and the ST from the packet data comprises:
 storing the TDM data, STs, and RTs in order from small to large STs, with one to one correspondence maintained among the TDM data, the STs, and the RTs.   
   
   
       4 . The method of  claim 1 , wherein determining whether a difference between the current ST and the current RT is a mutated value comprises:
 comparing an amplitude of a difference between the current receiver/sender timestamp difference and an average receiver/sender timestamp difference with a predetermined range to determine whether the amplitude exceeds the predetermined range;   if yes, detecting whether amplitudes of differences between subsequent N receiver/sender timestamp differences and the average receiver/sender timestamp difference exceed the range;   if the amplitudes of differences between the subsequent N receiver/sender timestamp differences and the average receiver/sender timestamp difference do not exceed the predetermined range, determining that the current receiver/sender timestamp difference is a mutated value   
   
   
       5 . The method of  claim 4 , wherein the pre-processing the ST and RT comprises:
 replacing the current receiver/sender timestamp difference with the average receiver/sender timestamp difference.   
   
   
       6 . The method of  claim 1 , wherein acquiring a service clock according to the pre-processed ST and RT comprises:
 determining an amplitude of a frequency difference or phase difference between an output clock signal and a received clock signal according to the pre-processed ST and RT;   performing smooth filtering on the frequency difference or phase difference between the output clock signal and the received clock signal;   performing an inversed phase modulation on a frequency or phase of the output clock signal according to the frequency difference or phase difference after the smooth filtering;   fixating the amplitude of the frequency difference or phase difference between the clock signal and the received clock signal, and   recovering the service clock at the sending end.   
   
   
       7 . A device for improving clock stability, comprising:
 a determining unit, configured to determine whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value;   a processing unit, configured to pre-process the ST and RT according to a determination result from the determining unit; and   a service clock acquiring unit, configured to acquire a service clock according to the pre-processed ST and RT from the processing unit.   
   
   
       8 . The device for improving clock stability of  claim 7 , wherein the determining unit comprises a receiving subunit, a detecting subunit and a determining subunit;
 the receiving subunit is configured to receive current timestamps comprising an ST and an RT;   the detecting subunit is configured to detect whether an amplitude of a difference between a current receiver/sender timestamp difference and an average receiver/sender timestamp difference is within a predetermined range according to the ST and the RT received by the receiving subunit and the average receiver/sender timestamp difference stored in the detecting subunit and send a detection result to the determining subunit; and   the determining subunit is configured to determine whether the current receiver/sender timestamp difference is a mutated value according to the detection result from the detecting subunit.   
   
   
       9 . The device for improving clock stability of  claim 8 , wherein the processing unit comprises a difference processing subunit, configured to compute an average receiver/sender timestamp difference according to the determination result from the determining subunit and update the average receiver/sender timestamp difference stored in the detecting subunit. 
   
   
       10 . The device for improving clock stability of  claim 8 , wherein the processing unit comprises:
 a difference replacing subunit, configured to replace the current receiver/sender timestamp difference by the average receiver/sender timestamp difference stored in the detecting subunit when the determination result from the determining subunit is that the current receiver/sender timestamp difference is a mutated value; and   an average difference subunit, configured to compute an average receiver/sender timestamp difference according to the current receiver/sender timestamp difference replaced by the difference replacing subunit and update the average receiver/sender timestamp difference stored in the detecting subunit when the determination result from the determining subunit is that the current receiver/sender timestamp difference is a mutated value, or compute an average receiver/sender timestamp difference and update the average receiver/sender timestamp difference stored in the detecting subunit when the determination result from the determining subunit is that the current receiver/sender timestamp difference is not a mutated value.   
   
   
       11 . The device for improving clock stability of  claim 7 , wherein the service clock acquiring unit comprises:
 a phase discrimination subunit, configured to receive the pre-processed timestamps and determine an amplitude of a frequency difference or phase difference between an output clock signal and a received clock signal according to the pre-processed timestamps received;   a filtering subunit, configured to perform smooth filtering on the frequency difference or phase difference between the output clock signal and the received clock signal from the phase discrimination subunit; and   a phase modulation subunit, configured to perform an inversed phase modulation on the frequency or phase of the output clock signal according to the frequency difference or phase difference output from the filtering subunit, and fixate the amplitude of the frequency difference or phase difference between the output clock signal and the received clock signal.   
   
   
       12 . The device for improving clock stability of  claim 7 , further comprising a data receiving unit and a data sending unit, wherein:
 the data receiving unit is configured to receive packet data, record the current RT, separate TDM data and the current ST, send the TDM data to the data sending unit, and send the ST and the RT to the determining unit; and   the data sending unit is configured to send the TDM data received from the data receiving unit according to the service clock acquired by the service clock acquiring unit.   
   
   
       13 . A computer-readable medium having computer usable instructions stored thereon for execution by a processor to perform a method comprising:
 determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value;   pre-processing the ST and RT, if the difference between the ST and RT is a mutated value;   acquiring a service clock according to the pre-processed ST and RT; and   sending time division multiplex (TDM) data according to the service clock.