Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof

Abstract

A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.

1 . A nonvolatile ferroelectric memory device comprising:
 a silicon substrate;   an insulating layer formed in an etching region of the silicon substrate;   a floating channel layer formed over the insulating layer;   an impurity layer formed at both ends of the floating channel layer, the impurity layer including a source region formed over the insulating layer and a drain region formed over the silicon substrate;   a ferroelectric layer formed over the floating channel layer; and   a word line formed over the ferroelectric layer.   
   
   
       2 . The nonvolatile ferroelectric memory device according to  claim 1 , wherein the silicon substrate comprises a P-type substrate. 
   
   
       3 . The nonvolatile ferroelectric memory device according to  claim 1 , wherein the drain region is connected to a bulk connection silicon region to expose a part of the silicon substrate. 
   
   
       4 . The nonvolatile ferroelectric memory device according to  claim 3 , wherein the bulk connection silicon region is formed to have substantially the same height as that of the insulating layer. 
   
   
       5 . The nonvolatile ferroelectric memory device according to  claim 1 , further comprising a sensing line contact and a bit line contact, the sensing line and the bit line being formed over the impurity layer and arranged alternately with the word line. 
   
   
       6 . The nonvolatile ferroelectric memory device according to  claim 1 , further comprising a bit line formed over the drain region and at a top side of the silicon substrate where the insulating layer is not formed. 
   
   
       7 . The nonvolatile ferroelectric memory device according to  claim 1 , further comprising a sensing line formed over the source region and at a top side of the insulating layer where the silicon substrate is not formed. 
   
   
       8 . The nonvolatile ferroelectric memory device according to  claim 1 , wherein the impurity layer comprises an N+ layer. 
   
   
       9 . The nonvolatile ferroelectric memory device according to  claim 1 , further comprising a buffer insulating layer formed between the floating channel layer and the ferroelectric layer. 
   
   
       10 . The nonvolatile ferroelectric memory device according to  claim 9 , further comprising a floating conductive layer formed between the buffer insulating layer and the floating channel layer. 
   
   
       11 . A nonvolatile ferroelectric memory device comprising:
 a memory cell comprising a silicon substrate including a floating channel layer formed over a bottom word line and drain/source regions formed at both ends of the floating channel layer;   a ferroelectric layer formed over the floating channel layer; and   a word line formed over the ferroelectric layer, wherein the memory cell is configured to induce a different channel resistance at a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so as to read/write data;   a register configured to store information of the memory cell; and   a refresh control unit configured to perform a refresh operation in a given refresh cycle using the information stored in the register, thereby improving retention characteristics of data stored in the memory cell.   
   
   
       12 . The nonvolatile ferroelectric memory device according to  claim 11 , wherein the memory cell has a 1T-FET type cell structure. 
   
   
       13 . The nonvolatile ferroelectric memory device according to  claim 11 , wherein the memory cell comprises:
 an insulating layer formed in an etching region of the silicon substrate;   a floating channel layer formed over the insulating layer; and   an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate.   
   
   
       14 . The nonvolatile ferroelectric memory device according to  claim 13 , wherein the silicon substrate comprises a P-type substrate. 
   
   
       15 . The nonvolatile ferroelectric memory device according to  claim 13 , wherein the drain region is connected to a bulk connection silicon region, thereby exposing a part of the silicon substrate. 
   
   
       16 . The nonvolatile ferroelectric memory device according to  claim 15 , wherein the bulk connection silicon region is formed to have substantially the same height as that of the insulating layer. 
   
   
       17 . The nonvolatile ferroelectric memory device according to  claim 13 , further comprising a sensing line contact and a bit line contact, the sensing line and the bit line being formed over the impurity layer and arranged alternately with the word line in a zigzag form. 
   
   
       18 . The nonvolatile ferroelectric memory device according to  claim 13 , further comprising a bit line formed over the drain region and at a top side of the silicon substrate where the insulating layer is not formed. 
   
   
       19 . The nonvolatile ferroelectric memory device according to  claim 13 , further comprising a sensing line formed over the source region and at a top side of the insulating layer where the silicon substrate is not formed. 
   
   
       20 . The nonvolatile ferroelectric memory device according to  claim 13 , wherein the impurity layer comprises an N+ layer. 
   
   
       21 . The nonvolatile ferroelectric memory device according to  claim 11 , further comprising a buffer insulating layer formed between the floating channel layer and the ferroelectric layer. 
   
   
       22 . The nonvolatile ferroelectric memory device according to  claim 21 , further comprising a floating conductive layer formed between the buffer insulating layer and the floating channel layer. 
   
   
       23 - 52 . (canceled)