Vertical semiconductor device, dram device including the same

Abstract

A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

1 . A vertical semiconductor device, comprising:
 single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion;   a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate;   a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies;   a first impurity region in the upper surface of the substrate under the active bodies; and   a second impurity region in the second active portion.   
   
   
       2 . The vertical semiconductor device as claimed in  claim 1 , wherein the active bodies are formed by a laser epitaxial process. 
   
   
       3 . The vertical semiconductor device as claimed in  claim 1 , wherein the first width is about 5 nm to about 30 nm. 
   
   
       4 - 14 . (canceled) 
   
   
       15 . A DRAM device, comprising:
 single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion;   a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate;   a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, and the gate electrode being usable with a word line;   a first impurity region in the upper surface of the substrate under the active bodies;   a second impurity region in the second active portion;   a bit line structure electrically connected to the first impurity region; and   a capacitor electrically connected to the second impurity region.   
   
   
       16 . The DRAM device as claimed in  claim 15 , wherein the first width is about 5 nm to about 30 nm. 
   
   
       17 . The DRAM device as claimed in  claim 15 , wherein the substrate has an isolation region and an active region, and the active region has an extending direction at an angle of no more than about 90° with respect to the gate electrode. 
   
   
       18 . The DRAM device as claimed in  claim 15 , further comprising a protecting layer covering an upper surface and an upper sidewall of the active bodies. 
   
   
       19 - 20 . (canceled)