Cmos imager and system with selectively silicided gates

Abstract

The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

1 - 86 . (canceled) 
   
   
       87 . A CMOS imager, comprising:
 an array of pixels, at least one pixel comprising:
 a photo-collection region to accumulate photo-generated charge, wherein silicide is substantially absent from a surface of the photo-collection region; and 
 a transfer transistor to transfer the charge from the photo-collection region to a storage node, wherein the transfer transistor includes a polysilicon transfer gate comprising silicide and the storage node is substantially free of silicide. 
   
   
   
       88 . The CMOS imager of  claim 87 , further comprising a readout circuit coupled to the array to receive an output signal corresponding to the charge on the node. 
   
   
       89 . The CMOS imager of  claim 87 , wherein the at least one pixel further comprises a reset transistor coupled to the node, wherein the reset transistor includes a polysilicon reset gate comprising opaque silicide. 
   
   
       90 . The CMOS imager of  claim 89 , wherein the at least one pixel further comprises a row select transistor coupled in series with a source follower transistor, wherein the source follower transistor includes a polysilicon source follower gate comprising opaque silicide coupled to the node. 
   
   
       91 . The CMOS imager of  claim 89 , wherein the transfer gate and the reset gate further comprise a barrier metal portion. 
   
   
       92 . The CMOS imager of  claim 87 , wherein the silicide comprises a refractory metal. 
   
   
       93 . The CMOS imager of  claim 87 , wherein the transfer gate comprises a barrier metal layer. 
   
   
       94 . The CMOS imager of  claim 87 , wherein a photogate is formed over the photo-collection region and silicide is substantially absent from a surface of the photogate. 
   
   
       95 . The CMOS imager of  claim 88 , wherein the readout circuit is configured to provide correlated sampling of signals from the pixel. 
   
   
       96 . The CMOS imager of  claim 95 , wherein the silicide comprises a refractory metal. 
   
   
       97 . The CMOS imager of  claim 96 , further comprising an analog-to-digital converter for producing digital signals from analog signals from pixels of the array, and image processing circuitry for processing said digital signals. 
   
   
       98 . The CMOS imager of  claim 87 , further comprising a load transistor coupled to a ground source, wherein the at least one pixel further comprises a source follower transistor coupled in series with the load transistor, wherein the source follower transistor includes a polysilicon source follower gate comprising opaque silicide coupled to the node. 
   
   
       99 . The CMOS imager of  claim 87 , further comprising:
 a readout circuit configured to provide correlated sampling of the pixel;   an analog-to-digital converter; and   image processing circuitry,   wherein the storage node is a floating diffusion node, the polysilicon transfer gate is adjacent to the photo-collection region and to the floating diffusion node, and the at least one pixel of the array, further comprises:
 a reset transistor, including a polysilicon reset gate, coupled to the floating diffusion node and to an n+ diffusion region configured to be coupled to a voltage source, the reset transistor configured to transfer voltage from the voltage source to the floating diffusion node; 
 a source follower transistor, including a polysilicon source follower gate, coupled to the floating diffusion node; and 
 silicide located on a surface of each one of the polysilicon transfer gate, the polysilicon reset gate, and the polysilicon source follower gate, and being substantially absent from a surface of the floating diffusion node. 
   
   
   
       100 . The CMOS imager of  claim 99 , further comprising a load transistor coupled to a row select transistor and a ground source. 
   
   
       101 . The CMOS imager of  claim 87 , further comprising:
 a readout circuit configured to provide correlated sampling of each pixel;   an analog-to-digital converter; and   image processing circuitry,   wherein the transfer transistor has a surface of a source/drain region substantially free of silicide, and the at least one pixel of the array, further comprises:
 a shallow trench isolation region; 
 a reset transistor coupled between the storage node and a voltage source, the reset transistor having a silicided gate and having a surface of a source/drain region substantially free of silicide; and 
 a source follower transistor having a silicided gate coupled to the storage node and having a surface of a source/drain region substantially free of silicide. 
   
   
   
       102 . The CMOS imager of  claim 101 , further comprising a load transistor coupled to a row select transistor. 
   
   
       103 . A camera system, comprising:
 a bus;   a processor;   random access memory coupled to the processor via the bus;   a CMOS imager coupled to the processor via the bus, the imager comprising an array of pixels, each pixel containing silicided transistor gates, transistor source/drain regions free from silicide, a photodiode, and shallow trench isolation, the imager configured to perform correlated sampling of each pixel, analog-to-digital conversion of the output of each pixel, and image processing.   
   
   
       104 . A camera system, comprising:
 a processor;   random access memory coupled to the processor;   a non-volatile memory subsystem coupled to the processor and configured to enable use of removable storage media; and   a CMOS imager, coupled to the processor, comprising a pixel array having silicided gates of transistors, unsilicided source/drain regions of the transistors, and an analog-to-digital converter.   
   
   
       105 . The system of  claim 104 , wherein the silicided transistors include a plurality of silicided transfer transistors and the CMOS imager further comprises a readout circuit configured to provide correlated sampling. 
   
   
       106 . The system of  claim 105 , wherein the silicided transistors include a refractory metal. 
   
   
       107 . The system of  claim 106 , wherein the silicided transistors include a barrier metal layer. 
   
   
       108 . The system of  claim 104 , wherein the silicided transistors include a refractory metal. 
   
   
       109 . The system of  claim 104 , wherein the CMOS imager further comprises image processing circuitry for processing signals derived from the pixel array. 
   
   
       110 . The system of  claim 104 , wherein the removable storage media includes optical storage media. 
   
   
       111 . The system of  claim 110 , wherein the silicided transistors include a plurality of silicided transfer transistors and the CMOS imager further comprises a readout circuit configured to provide correlated sampling of pixels of the pixel array, and image processing circuitry for processing signals derived from said readout circuit.