Verification of chipset firmware updates

Abstract

In general, in one aspect, the disclosure describes an apparatus that includes updatable non-volatile memory to store firmware and non-updateable non-volatile memory to store an interrupt sequence. The apparatus includes a chip interface to receive an interrupt instruction from management firmware. Receipt of the interrupt instruction controls access to and initiation of the interrupt sequence. After initiation of the interrupt sequence the apparatus may receive a firmware update and/or validate the firmware is from a valid source. The validation of the firmware may include utilizing the management firmware to verify the cryptographic signature for the firmware.

1 . An apparatus comprising
 updatable non-volatile memory to store apparatus firmware;   non-updateable non-volatile memory to store an interrupt sequence; and   a chip interface to receive of an interrupt instruction, wherein the receipt of the interrupt instruction is to control access to the interrupt sequence.   
   
   
       2 . The apparatus of  claim 1 , wherein the interrupt sequence is to run upon receipt of the interrupt instruction. 
   
   
       3 . The apparatus of  claim 2 , wherein the interrupt instruction is to be received from a processor running management firmware. 
   
   
       4 . The apparatus of  claim 3 , wherein the apparatus is to await further instruction from the management firmware after running the interrupt sequence. 
   
   
       5 . The apparatus of  claim 3 , wherein the updatable non-volatile memory is to receive and store updated apparatus firmware after running the interrupt sequence. 
   
   
       6 . The apparatus of  claim 5 , wherein the updatable non-volatile memory is to request validation of the updated apparatus firmware after the updated apparatus firmware is stored. 
   
   
       7 . The apparatus of  claim 6 , wherein the updatable non-volatile memory is to transmit the updated apparatus firmware to the management firmware to verify a cryptographic signature for the updated apparatus firmware. 
   
   
       8 . A method comprising
 receiving an interrupt instruction from management firmware running on a processor, wherein the interrupt instruction is received on a chip interface;   running an interrupt sequence contained in a non-updateable portion of non-volatile memory, wherein the interrupt sequence interrupts operation of apparatus firmware running from an updateable portion of the non-volatile memory; and   receiving an additional instruction from the management firmware.   
   
   
       9 . The method of  claim 8 , wherein the receiving an additional instruction includes initiating an update sequence to receive an apparatus firmware update. 
   
   
       10 . The method of  claim 9 , wherein the initiating an update sequence includes receiving the apparatus firmware update from an operating system and storing the apparatus firmware update in the updateable portion of the non-volatile memory. 
   
   
       11 . The method of  claim 8 , wherein the receiving an additional instruction includes initiating a validation sequence to validate the firmware update. 
   
   
       12 . The method of  claim 11 , wherein the initiating a validation sequence includes
 providing at least a portion of the apparatus firmware and a cryptographic signature for at least a portion of the apparatus firmware to the management firmware to verify the apparatus firmware cryptographic signature, and   receiving a verification status from the management firmware.   
   
   
       13 . The method of  claim 8 , further comprising providing a public key to the management firmware, wherein the public key is used to verify a cryptographic signature for the firmware. 
   
   
       14 . The method of  claim 13 , wherein the providing a public key includes providing the public key from the apparatus firmware upon initial platform boot. 
   
   
       15 . The method of  claim 8 , wherein the receiving an interrupt instruction is in response to receiving notification that a firmware update is available. 
   
   
       16 . A system comprising
 a processor to run management firmware, wherein the management firmware includes a configuration register to store a public key of a public private key pair used to generate a cryptographic signature; and   at least one integrated circuit (IC) to run IC firmware, wherein the IC includes updatable non-volatile memory to store the IC firmware and a cryptographic signature for the IC firmware and non-updateable non-volatile memory to store an interrupt sequence, wherein the IC includes a chip interface to receive an interrupt instruction from the management firmware, wherein the receipt of the interrupt instruction is to control access to the interrupt sequence.   
   
   
       17 . The system of  claim 16 , wherein the management firmware provides the interrupt instruction when IC firmware updates are available and instructs the IC to initiate an update sequence after the interrupt sequence is performed. 
   
   
       18 . The system of  claim 16 , wherein the management firmware provides the interrupt instruction when IC firmware updates are complete and instructs the chipset to initiate a validation sequence after the interrupt sequence is performed. 
   
   
       19 . The system of  claim 16 , wherein the public key is burned in the configuration register during manufacturing. 
   
   
       20 . The system of  claim 16 , wherein the public key is provided to the management firmware during initial system boot up.