Method and apparatus for error detection and correction

Abstract

A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

1 - 32 . (canceled) 
   
   
       33 . In a memory system comprising:
 a data memory comprising a plurality of memory cells arranged in a plane of m rows and n columns, each cell adapted to store a respective one of m×n data bits during a write access cycle and to retrieve said one bit during a read access cycle;   a write access circuit connected to the data memory to store, during said write access cycle, each of n new data bits into a respective one of the n cells comprising a first row of said m rows; and   a read access circuit connected to the data memory to retrieve, during said read access cycle, each of n old data bits stored in a respective one of the n cells comprising said first row of said m rows;   
     a method comprising the steps of:
 storing n old parity bits; 
 receiving all of the n new data bits; 
 retrieving all of the n old data bits; 
 comparing each of the n new data bits to a corresponding one of the n old data bits; and 
 if and only if a respective x th  one of the n new data bits is different from the corresponding x th  one of the n old data bits, selectively changing the respective x th  one of said n old parity bits. 
 
   
   
       34 . The method of  claim 33  further comprising the steps of:
 generating n new parity bits, each based only on the m old data bits comprising a respective one of the n columns;   comparing each of the new parity bits to a respective one of the old parity bits; and   if and only if a y th  one of the new parity bits is different from the y th  one of the old parity bits, providing a first error signal to indicate that one of the m old data bits has an error.   
   
   
       35 . The method of  claim 34  further comprising the step of:
 correcting each of the m old data bits indicated by said first error signal as being in error.   
   
   
       36 . The method of  claim 35  further comprising the steps of:
 providing a second error signal to indicate that an x th  one of the n old data bits comprising said selected first row of said data memory has an error; and   correcting each of the old data bits indicated by said second error signal as being in error.   
   
   
       37 . The method of  claim 35  further comprising the step of:
 providing a third error signal to indicate which of more than one of the n old data bits comprising said selected first row of said data memory have errors; and   correcting each of the old data bits indicated by said third error signal as being in error.   
   
   
       38 . The method of  claim 33  further comprising the step of:
 initializing all of said m×n data bits and all of said parity bits to selected predetermined values prior to operation of the system.   
   
   
       39 . In a memory system comprising:
 a data memory comprising a plurality of memory cells arranged in a plane of m rows and n columns, each cell adapted to store a respective one of m×n data bits during a write access cycle and to retrieve said one bit during a read access cycle;   a write access circuit connected to the data memory to store, during said write access cycle, each of n new data bits into a respective one of the n cells comprising a first row of said m rows; and   a read access circuit connected to the data memory to retrieve, during said read access cycle, each of n old data bits stored in a respective one of the n cells comprising said first row of said m rows;   
     a method comprising the steps of:
 storing n old s-bit check words; 
 receiving all of the n new data bits; 
 comparing each of the n new data bits to a corresponding one of the n old data bits; and 
 if and only if an N th  one of the new data bits is different from the N th  one of the old data bits, toggling a selected subset of the s bits of the N th  old check word. 
 
   
   
       40 . The method of  claim 39  further comprising the steps of:
 generating n new s-bit check words, each based only on the m old data bits comprising a respective one of the n columns;   comparing each of the new check words to a respective one of the old check words; and   if and only if a y th  one of the new check words is different from the y th  one of the old check words, providing a first error signal to indicate which of the m old data bits have errors.   
   
   
       41 . The method of  claim 40  further comprising the step of:
 correcting each of the m old data bits indicated by said first error signal as being in error.   
   
   
       42 . The method of  claim 41  further comprising the steps of:
 providing a second error signal to indicate that an x th  one of the n old data bits comprising said selected first row of said data memory has an error; and   correcting the x th  old data bit indicated by said second error signal as being in error.   
   
   
       43 . The method of  claim 41  further comprising the step of:
 providing a third error signal to indicate which of more than one of the n old data bits comprising said selected first row of said data memory have errors; and   correcting each of the n old data bits indicated by said third error signal as being in error.   
   
   
       44 . The method of  claim 39  further comprising the step of:
 initializing all of said m×n data bits and all of said s×n check bits to selected predetermined values prior to operation of the system.   
   
   
       45 . A method for operating a memory system adapted to store m old n-bit data words as an array of m rows by n columns of data bits, the method comprising the steps of:
 storing n old s-bit check words;   receiving a new n-bit data word selected to replace the M th  old data word;   comparing each of the bits of the new data word to a corresponding one of the bits of the M th  old data word; and   if and only if an N th  one of the bits of the new data word is different from the N th  bit of the M th  old data word, toggling a selected subset of the s bits of the N th  old check word.   
   
   
       46 . The method of  claim 45  further comprising the steps of:
 generating n new s-bit check words, each based only on a respective one of the n columns of m old data bits;   comparing each of the new check words to a respective one of the old check words; and   if and only if a y th  one of the new check words is different from the y th  one of the old check words, providing a first error signal to indicate which of the m old data bits in the y th  column have errors.   
   
   
       47 . The method of  claim 46  further comprising the step of:
 correcting each of the m old data bits indicated by said first error signal as being in error.   
   
   
       48 . The method of  claim 47  further comprising the steps of:
 providing a second error signal to indicate that an x th  one of the n old data bits comprising said M th  old data word has an error; and   correcting the x th  old data bit indicated by said second error signal as being in error.   
   
   
       49 . The method of  claim 47  further comprising the step of:
 providing a third error signal to indicate which of more than one of the n old data bits comprising said M th  old data word have errors; and   correcting each of the n old data bits indicated by said third error signal as being in error.   
   
   
       50 . The method of  claim 45  further comprising the step of:
 initializing all of said m×n data bits and all of said s×n check bits to selected predetermined values prior to operation of the system.