Ferroelectric memory device

Abstract

A ferroelectric memory device having plural memory cells, each composed of a memory cell transistor and a memory cell capacitor including a lower electrode that is independent for each memory cell capacitor, a ferroelectric layer formed on the lower electrode, and an upper electrode layer formed on the ferroelectric layer. A plurality of the upper electrode layers are connected together and constitute a plate electrode, and the width of the upper electrode is narrower than the width of the ferroelectric layer. Accordingly, by making the width of the upper electrode narrower than the width of the ferroelectric layer, it is possible to prevent current leakage between the upper electrode and the lower electrode, which reduces the placement interval of the memory cell capacitors without causing current leakage between the upper electrode and the lower electrode, and results in a smaller memory cell size.

1 - 15 . (canceled) 
   
   
       16 . A ferroelectric memory device comprising a plurality of memory cells, each memory cell of the plurality of memory cells including a respective memory cell capacitor, and the plurality of memory cells being arranged in a plane having a first direction and along a second direction that is substantially perpendicular to the first direction,
 wherein each respective memory cell capacitor of the plurality of memory cells comprises:   a lower electrode;   a ferroelectric layer formed on an upper surface of the lower electrode; and   an upper electrode formed on an upper surface of the ferroelectric layer,   wherein the lower electrode of each respective memory cell capacitor is independent from the lower electrodes of other memory cell capacitors, such that each respective memory cell capacitor includes a separate lower electrode,   wherein each respective upper electrode of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction forms a continuous plate electrode covering the respective independent lower electrode of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction, and   wherein the width of each respective upper electrode in the first direction is narrower than the width of each respective ferroelectric layer in the first direction.   
   
   
       17 . The ferroelectric memory device of  claim 16 ,
 wherein the lower electrode is electrically connected to a bit line.   
   
   
       18 . The ferroelectric memory device of  claim 16 ,
 wherein each respective ferroelectric layer of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction forms a continuous plate electrode covering the respective independent lower electrode of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction.   
   
   
       19 . The ferroelectric memory device of  claim 16 ,
 wherein the plurality of memory cells are arranged in a matrix.   
   
   
       20 . The ferroelectric memory device of  claim 16 ,
 wherein each memory cell includes a respective memory cell transistor.   
   
   
       21 . The ferroelectric memory device of  claim 16 ,
 wherein the width of each respective independent lower electrode in the first direction is narrower than the width of each respective ferroelectric layer in the first direction.   
   
   
       22 . The ferroelectric memory device of  claim 21 ,
 wherein the width of each respective upper electrode in the first direction and the width of each respective independent lower electrode in the first direction are substantially the same, and   wherein a position of both edges along the second direction of each respective upper electrode and a position of both edges along the second direction of each respective independent lower electrode are substantially the same.   
   
   
       23 . The ferroelectric memory device of  claim 21 ,
 wherein the width of each respective upper electrode in the first direction and the width of each respective independent lower electrode in the first direction are substantially the same, and   wherein a position of both edges along the second direction of each respective upper electrode and a position of both edges along the second direction of each respective independent lower electrode are different from each other.   
   
   
       24 . The ferroelectric memory device comprising a plurality of memory cells, each memory cell of the plurality of memory cells including a respective memory cell capacitor, and the plurality of memory cells being arranged in a plane having a first direction and along a second direction that is substantially perpendicular to the first direction,
 wherein each respective memory cell capacitor of the plurality of memory cells comprises:   a lower electrode;   a ferroelectric layer formed on an upper surface of the lower electrode; and   an upper electrode formed on an upper surface of the ferroelectric layer,   wherein the lower electrode of each respective memory cell capacitor is independent from the lower electrodes of other memory cell capacitors, such that each respective memory cell capacitor includes a separate lower electrode,   wherein each respective upper electrode of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction forms a continuous plate electrode covering the respective independent lower electrode of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction, and   wherein the width of each respective upper electrode in the first direction is narrower than the width of each respective lower electrode in the first direction.   
   
   
       25 . The ferroelectric memory device of  claim 24 ,
 wherein the lower electrode is electrically connected to a bit line.   
   
   
       26 . The ferroelectric memory device of  claim 24 ,
 wherein each respective ferroelectric layer of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction forms a continuous plate electrode covering the respective independent lower electrode of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction.   
   
   
       27 . The ferroelectric memory device of  claim 24 ,
 wherein the plurality of memory cells are arranged in a matrix.   
   
   
       28 . The ferroelectric memory device of  claim 24 ,
 wherein each memory cell includes a respective memory cell transistor.   
   
   
       29 . The ferroelectric memory device of  claim 24 ,
 wherein the width of each respective independent lower electrode in the first direction is narrower than the width of each respective ferroelectric layer in the first direction.   
   
   
       30 . The ferroelectric memory device of  claim 29 ,
 wherein the width of each respective upper electrode in the first direction and the width of each respective independent lower electrode in the first direction are substantially the same, and   wherein a position of both edges along the second direction of each respective upper electrode and a position of both edges along the second direction of each respective independent lower electrode are substantially the same.   
   
   
       31 . The ferroelectric memory device of  claim 29 ,
 wherein the width of each respective upper electrode in the first direction and the width of each respective independent lower electrode in the first direction are substantially the same, and   wherein a position of both edges along the second direction of each respective upper electrode and a position of both edges along the second direction of each respective independent lower electrode are different from each other.