Memory protection system and method

Abstract

A memory protection method is provided with a user input key: The user input key is compared with an internal private key in a memory security circuit having an integral connection with a solid-state memory for controlling data flow therefrom.

1 . A memory protection method comprising:
 providing a user input key; and   comparing the user input key with an internal private key in a memory security circuit having an integral connection with a solid-state memory for controlling data flow therefrom.   
   
   
       2 . The method as claimed in  claim 1  further comprising:
 erasing the internal private key to keep the solid-state memory unlocked.   
   
   
       3 . The method as claimed in  claim 1  further comprising:
 providing a new user input key different from the internal private key to keep the solid-state memory locked.   
   
   
       4 . The method as claimed in  claim 1  further comprising:
 erasing the internal private key;   writing a new internal private key; and   accessing the solid-state memory with the new internal private key.   
   
   
       5 . The method as claimed in  claim 1  further comprising:
 inputting an incorrect user input key a predetermined number of times; and   erasing the solid-state memory when the predetermined number of times is exceeded.   
   
   
       6 . A memory protection method comprising:
 inputting and outputting a plurality of input and output signals through an input/output control circuit to provide a user input key, an internal private key, and data;   storing the user input key and the internal private key in storage having an integral connection to the input/output control circuit;   comparing the user input key and the internal private key in a logic circuit having an integral connection to the storage;   controlling a control circuit when the user input key and the internal private key match to output an enable signal to a solid-state memory having an integral connection to the control circuit; and   outputting the data to the input/output control circuit from the solid-state memory in response to the enable signal.   
   
   
       7 . The method as claimed in  claim 6  further comprising:
 erasing the internal private key to keep the solid-state memory unlocked when power is turned off and on.   
   
   
       8 . The method as claimed in  claim 6  further comprising:
 writing a new user input key different from the internal private key to keep the solid-state memory locked while power is on.   
   
   
       9 . The method as claimed in  claim 6  further comprising:
 erasing the internal private key;   erasing the solid-state memory and the user input key when the internal private key is erased;   writing a new internal private key; and   accessing the solid-state memory with the new internal private key.   
   
   
       10 . The method as claimed in  claim 6  further comprising:
 inputting an incorrect user input key a predetermined number of times;   erasing the solid-state memory when the predetermined number of times is exceeded;   writing a new internal private key; and   accessing the solid-state memory with the new internal private key.   
   
   
       11 . A memory protection system comprising:
 a user input key storage;   an internal private key storage;   a comparator having integral connections with the user input key storage and the internal private key storage; and   a solid-state memory having an integral connection with the comparator for allowing access to data therein when the contents of the internal private key storage and the user input key storage match.   
   
   
       12 . The system as claimed in  claim 11  further comprising:
 circuitry for erasing the internal private key to keep the solid-state memory unlocked.   
   
   
       13 . The system as claimed in  claim 11  further comprising:
 circuitry for providing a new user input key different from the internal private key to keep the solid-state memory locked.   
   
   
       14 . The system as claimed in  claim 11  further comprising:
 circuitry for erasing the internal private key;   circuitry for writing a new internal private key; and   circuitry for accessing the solid-state memory with the new internal private key.   
   
   
       15 . The system as claimed in  claim 11  further comprising:
 circuitry for inputting an incorrect user input key a predetermined number of times; and   circuitry for erasing the solid-state memory when the predetermined number of times is exceeded.   
   
   
       16 . A memory protection system comprising:
 an input/output control circuit for inputting and outputting a plurality of input and output signals to provide a user input key, an internal private key, and data;   registers for storing the user input key and the internal private key, the registers having an integral connection to the input/output control circuit;   a logic circuit for comparing the user input key and the internal private key, the logic circuit having an integral connection to the registers;   a control circuit for outputting an enable signal when the user input key and the internal private key match, the control circuit having an integral connection to the logic circuit; and   a solid-state memory for outputting the data to the input/output control circuit in response to the enable signal, the solid-state memory having an integral connection to the control circuit.   
   
   
       17 . The system as claimed in  claim 16  further comprising:
 circuitry for erasing the internal private key to keep the solid-state memory) unlocked when power is turned off and on.   
   
   
       18 . The system as claimed in  claim 16  further comprising:
 circuitry for writing a new user input key different from the internal private key to keep the solid-state memory locked while power is on.   
   
   
       19 . The system as claimed in  claim 16  further comprising:
 circuitry for erasing the internal private key;   circuitry for erasing the solid-state memory and the user input key when the internal private key is erased;   circuitry for writing a new internal private key; and   circuitry for accessing the solid-state memory with the new internal private key.   
   
   
       20 . The system as claimed in  claim 16  further comprising:
 circuitry for inputting an incorrect user input key a predetermined number of times;   circuitry for erasing the solid-state memory when the predetermined number of times is exceeded;   circuitry for writing a new internal private key; and   accessing the solid-state memory with the new internal private key.