US2010095094A1PendingUtilityA1

Method for processing data

54
Assignee: VORBACH MARTINPriority: Jun 20, 2001Filed: Dec 17, 2009Published: Apr 15, 2010
Est. expiryJun 20, 2021(expired)· nominal 20-yr term from priority
G06F 8/45G06F 15/7867
54
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Claims

Abstract

A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

Claims

exact text as granted — not AI-modified
1 . A method for translating a program for a system including at least one first processor and a reconfigurable unit, the method comprising:
 determining from the program, code portions of the program suitable for the reconfigurable unit; and   at least one of extracting and separating, remaining code of the program for processing by the first processor.   
   
   
       2 . The method as recited in  claim 1 , further comprising:
 appending interface code to the code portions extracted for the first processor to permit communication between the first processor and the reconfigurable unit according to the system.   
   
   
       3 . The method as recited in  claim 1 , further comprising:
 appending interface to the code portions extracted for the reconfigurable unit so that communication is enabled between the first processor and the reconfigurable unit according to the system.   
   
   
       4 . The method as recited in  claim 1 , wherein the determining step includes determining the code portions based on automated analyses. 
   
   
       5 . The method as recited in  claim 1 , wherein the program includes instructions defining the code portions to be extracted, and wherein the method further comprises automatically analyzing the instructions. 
   
   
       6 . The method as recited in  claim 1 , wherein the code portions to be extracted are determined based on calls of subprograms. 
   
   
       7 . The method as recited in  claim 1 , further comprising:
 providing an interface code which provides at least one of memory linkage, register linkage, and linkage via a network.   
   
   
       8 . The method as recited in  claim 1 , further comprising:
 analyzing at least one of the extracted code portions and results achievable with a given extraction; and   restarting an extraction with new improved parameters based on the analysis.   
   
   
       9 . The method as recited in  claim 1 , further comprising:
 appending control code to the extracted code for at least one of management, control, and communication of the development system.   
   
   
       10 . The method as recited in  claim 1 , wherein the first processor has a conventional processor architecture, the architecture including at least one of a von-Neumann architecture, Harvard architecture, controller, CISC processor, RISC processor, VLIW processor, or DSP processor. 
   
   
       11 . The method as recited in  claim 1 , wherein the remaining code is extracted so that it is translatable via any ordinary unmodified compiler that is suitable for the first processor. 
   
   
       12 . A device for data processing, comprising:
 at least one conventional processor;   at least one reconfigurable unit; and   an arrangement configured to exchange data and status information between a conventional processor and a reconfigurable unit, the arrangement being configured so that the data and status information exchange is possible therebetween at least one of: i) during processing of one or more programs, ii) without having to interrupt data processing on the reconfigurable processor, and iii) without having to interrupt data processing on the conventional processor.

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