Semiconductor Devices Including Transistors Having Recessed Channels

Abstract

Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.

1 . A semiconductor device comprising:
 an isolation layer on a semiconductor substrate and defining an active region of the semiconductor substrate;   an upper gate electrode crossing over the active region and extending to the isolation layer;   a lower active gate electrode including a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode; and   a lower field gate electrode extending from the upper gate electrode to the isolation layer and having a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode.   
   
   
       2 . The semiconductor device of  claim 1 , further comprising a first impurity region and a second impurity region in an active region located on both sides of the first upper gate electrode. 
   
   
       3 . The semiconductor device of  claim 2 , wherein the first impurity region and the second impurity region have an asymmetric structure. 
   
   
       4 . The semiconductor device of  claim 2 , wherein the first impurity region has a shallow junction structure relative to a junction structure of the second impurity region. 
   
   
       5 . The semiconductor device of  claim 2 , wherein the first impurity region has an impurity density lower than an impurity density of the second impurity region. 
   
   
       6 . The semiconductor device of  claim 2 , further comprising a high density channel impurity region below the second impurity region, wherein the high density channel impurity region has a different conductivity type from conductivity types of the first and second impurity regions, and wherein the high density channel impurity region has an impurity density higher than an impurity density of a channel region below the first impurity region. 
   
   
       7 . The semiconductor device of  claim 2 , further comprising a data storage element electrically connected to the first impurity region. 
   
   
       8 . The semiconductor device of  claim 1 , wherein the upper gate electrode has a greater width than the widths of the first active gate electrode and the lower field gate electrode. 
   
   
       9 . A semiconductor device comprising:
 an isolation layer on a semiconductor substrate and defining an active region of the semiconductor substrate;   an upper gate electrode crossing over the active region and extending to the isolation layer;   a lower active gate electrode including a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode; and   a lower field gate electrode extending from the upper gate electrode to the isolation layer and having a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode.   wherein the lower field gate electrode comprises a first field gate electrode and a second field gate electrode below the first field gate electrode,   wherein the second field gate electrode has a greater width than a width of the first field gate electrode.   
   
   
       10 . The semiconductor device of  claim 9 , wherein the second field gate electrode has a greater width than a width of the first active gate electrode. 
   
   
       11 . The semiconductor device of  claim 9 , wherein the second field gate electrode is formed to cover the sidewalls of the active region located at both sides of the second active gate electrode as well as to cover the sidewalls of the active region located below the second active gate electrode. 
   
   
       12 . The semiconductor device of  claim 11 , wherein the second field gate electrode has a greater width than a width of the second active gate electrode. 
   
   
       13 . The semiconductor device of  claim 9 , wherein an upper surface of the second field gate electrode is higher than a bottom surface of the second active gate electrode. 
   
   
       14 . The semiconductor device of  claim 9 , further comprising a first impurity region and a second impurity region in an active region located on both sides of the first upper gate electrode. 
   
   
       15 . The semiconductor device of  claim 14 , wherein sidewalls of the active region of the first and second impurity regions do not overlap the lower field gate electrode. 
   
   
       16 . The semiconductor device of  claim 14 , wherein the first impurity region and the second impurity region have an asymmetric structure. 
   
   
       17 . A semiconductor device comprising:
 an isolation layer on a semiconductor substrate and defining an active region of the semiconductor substrate;   an upper gate electrode crossing over the active region and extending to the isolation layer;   a lower active gate electrode including a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode; and   a lower field gate electrode extending from the upper gate electrode to the isolation layer and having a bottom surface that is at a lower level than a bottom surface of the active gate electrode,   wherein the lower field gate electrode is disposed to overlap one of the sidewalls of the active region located on both sides of the lower active gate electrode and does not overlap the other of sidewalls of the active region located on both sides of the lower active gate electrode.   
   
   
       18 . The semiconductor device of  claim 17 , further comprising a first impurity region and a second impurity region in an active region located on both sides of the first upper gate electrode. 
   
   
       19 . The semiconductor device of  claim 18 , wherein the first impurity region does not overlap the lower field gate electrode. 
   
   
       20 . The semiconductor device of  claim 18 , further comprising a data storage element electrically connected to the first impurity region.