Non-volatile memory device and method of driving the same

Abstract

A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors.

1 . A non-volatile memory device, comprising:
 a memory cell array with a plurality of unit memory cells, the unit memory cells being arranged in a matrix pattern of rows and columns, each of the unit memory cells including:
 a first impurity diffusion region and a second impurity diffusion region in an active region of a semiconductor substrate, 
 first and second memory gates on the active region between the first impurity diffusion region and the second impurity diffusion region, the first and second memory gates corresponding to respective first and second memory transistors, and each of the first and second memory gates is adjacent to a respective one of the first and second impurity diffusion regions, 
 one select gate on the active region between the first and second memory gates, the select gate corresponding to a select transistor; 
 a third impurity diffusion region in the active region between the select gate and one of the first and second memory gates, and 
 a common source region in the active region between the select gate and the other one of the first and second memory gates; 
   a first word line coupled to control gates of the first memory transistors arranged in a column direction of the memory cell array;   a second word line coupled to control gates of the second memory transistors arranged in the column direction of the memory cell array;   a selection line coupled to gates of the selection transistors arranged in the column direction of the memory cell array; and   bit lines coupled to the first and second impurity diffusion regions.   
   
   
       2 . The non-volatile memory device as claimed in  claim 1 , wherein the first and second memory transistors are programmed in different ways from each other. 
   
   
       3 . The non-volatile memory device as claimed in  claim 1 , wherein one of the first and second memory transistors is a NOR type transistor, and the other one of the first and second memory transistors is a NAND type transistor. 
   
   
       4 . The non-volatile memory device as claimed in  claim 3 , wherein the selection transistor is on the active region between the NAND type transistor and the common source region. 
   
   
       5 . The non-volatile memory device as claimed in  claim 3 , wherein the NOR type transistor is programmed by Hot-carrier Injection (HCI) and the NAND type transistor is programmed by F-N (Flowler-Nordheim) tunneling. 
   
   
       6 . (canceled) 
   
   
       7 . The non-volatile memory device as claimed in  claim 1 , wherein at least one of the first and second memory transistors includes a first insulation layer, a charge storage layer, and a second insulation layer, and
 wherein the first insulation layer, the charge storage layer, and the second insulation layer are sequentially stacked between a semiconductor substrate on which the memory cell array is formed and the control gates of the first and second memory transistors.   
   
   
       8 . The non-volatile memory device as claimed in  claim 7 , wherein the charge storage layer includes a floating conductive layer or a charge trap type insulation layer. 
   
   
       9 . The non-volatile memory device as claimed in  claim 7 , wherein at least one of the first and second insulation layers includes a high dielectric thin layer. 
   
   
       10 . (canceled) 
   
   
       11 . The non-volatile memory device as claimed in  claim 1 , further comprising:
 first and second word lines connected to the first and second memory gates, respectively;   a select line connected to the select gate; and   first and second bit lines connected to the first and second impurity diffusion regions, respectively.   
   
   
       12 . A nonvolatile memory device having a plurality of memory cell units, the memory cell unit comprising:
 a first impurity diffusion region and a second impurity diffusion region in an active region of a semiconductor substrate;   first and second memory gates on the active region between the first impurity diffusion region and the second impurity diffusion region, the first and second memory gates each respectively adjacent to the first and second impurity diffusion regions;   one select gate on the active region between the first and second memory gates; and   first and second floating diffusion regions in the active region between the select gate and a corresponding one of the first and second memory gates,   wherein the first memory gate, the second memory gate, and the select gate correspond to a first memory transistor, a second memory transistor, and a select transistor, respectively, and   wherein the first memory transistor is configured to perform a first program operation performed by F-N (Flowler-Nordheim) tunneling, and the second memory transistor is configured to perform a second program operation by Hot-carrier Injection (HCI).