US2010109013A1PendingUtilityA1
Thin film transistor, method of manufacturing the same, and organic light emitting diode display device including the same
Est. expiryNov 4, 2028(~2.3 yrs left)· nominal 20-yr term from priority
H10D 86/441H10D 86/0223H10D 86/40H10D 86/0229H10K 59/131H10K 59/1213
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Claims
Abstract
A thin film transistor for an organic light emitting diode includes a substrate including a pixel portion and an interconnection portion, a buffer layer on the substrate, a gate electrode and a gate interconnection on the buffer layer, wherein the gate electrode is located at the pixel portion and the gate interconnection is located at the interconnection portion, a gate insulating layer on the substrate, a semiconductor layer on the gate electrode, source and drain electrodes electrically connected to the semiconductor layer, and a metal pattern on the gate interconnection.
Claims
exact text as granted — not AI-modified1 . A thin film transistor comprising:
a substrate including a pixel portion and an interconnection portion; a buffer layer on the substrate; a gate electrode and a gate interconnection on the buffer layer, the gate electrode being located at the pixel portion, the gate interconnection being located at the interconnection portion; a gate insulating layer on the substrate; a semiconductor layer on the gate electrode; source and drain electrodes electrically connected to the semiconductor layer; and a metal pattern on the gate interconnection.
2 . The thin film transistor of claim 1 , wherein the metal pattern includes the same material as the source and drain electrodes.
3 . The thin film transistor of claim 1 , wherein the source and drain electrodes and the metal pattern include at least one of molybdenum, chromium, tungsten, molybdenum-tungsten, aluminum, aluminum-neodymium, titanium, titanium nitride, copper, a molybdenum alloy, an aluminum alloy, and a copper alloy.
4 . The thin film transistor of claim 1 , further comprising an impurity-doped silicon layer between the semiconductor layer and the source and drain electrodes.
5 . The thin film transistor of claim 1 , wherein the semiconductor layer is a polysilicon layer.
6 . The thin film transistor of claim 1 , wherein the gate interconnection is in direct contact with the metal pattern.
7 . A method of manufacturing a thin film transistor, the method comprising:
providing a substrate having a pixel portion and a peripheral portion; forming a buffer layer on the substrate; forming a gate electrode and a gate interconnection on the buffer layer, the gate electrode being located at the pixel portion, the gate interconnection being located at the peripheral portion; forming a gate insulating layer on the gate electrode and the gate interconnection; forming an amorphous semiconductor layer and patterning the amorphous semiconductor layer to form a semiconductor layer pattern on the gate electrode of the pixel portion; forming a metal layer on the substrate to be electrically connected to the semiconductor layer pattern and the gate interconnection; applying an electric field to the metal layer to crystallize the semiconductor layer pattern to form a semiconductor layer; and patterning the metal layer to form source and drain electrodes electrically connected to the semiconductor layer of the pixel portion and a metal pattern on the gate interconnection.
8 . The method of claim 7 , wherein the metal pattern is in direct contact with the gate interconnection.
9 . The method of claim 7 , wherein the crystallization is performed by applying the electric field of about 100 V/cm 2 to about 10,000 V/cm 2 to the source/drain electrode metal layer.
10 . The method of claim 7 , wherein the metal layer is formed on the substrate to a thickness of about 50 nm to about 200 nm.
11 . The method of claim 7 , wherein the metal layer includes at least one of molybdenum, chromium, tungsten, molybdenum-tungsten, aluminum, aluminum-neodymium, titanium, titanium nitride, copper, a molybdenum alloy, an aluminum alloy, and a copper alloy.
12 . The method of claim 7 , further comprising forming an impurity-doped silicon layer between the semiconductor layer and the source and drain electrodes.
13 . An organic light emitting diode display device comprising:
organic light emitting diodes configured to emit light; and thin film transistors coupled to the organic light emitting diodes, each thin film transistor including:
a substrate having a pixel portion and an interconnection portion;
a buffer layer on the substrate;
a gate electrode and a gate interconnection on the buffer layer,
wherein the gate electrode is located at the pixel portion and a gate interconnection is located at the interconnection portion;
a gate insulating layer on the entire substrate;
a semiconductor layer on the gate electrode;
source and drain electrodes electrically connected to the semiconductor layer;
an insulating layer on the entire substrate;
a first electrode, the source and drain electrodes, an organic layer and a second layer on the insulating layer, wherein the first electrode is electrically connected to the source and drain electrodes, an organic layer and a second layer, and
a metal pattern on the gate interconnection.
14 . The organic light emitting diode display device of claim 13 , wherein the metal pattern includes the same material as the source and drain electrodes.
15 . The organic light emitting diode display device of claim 13 , further comprising an impurity-doped silicon layer disposed between the semiconductor layer and the source and drain electrodes.
16 . The organic light emitting diode display device of claim 13 , wherein the source and drain electrodes and the metal pattern include at least one of molybdenum, chromium, tungsten, molybdenum-tungsten, aluminum, aluminum-neodymium, titanium, titanium nitride, copper, a molybdenum alloy, an aluminum alloy, and a copper alloy.
17 . The organic light emitting diode display device of claim 13 , wherein the semiconductor layer is a polysilicon layer.
18 . The organic light emitting diode display device of claim 13 , wherein the gate interconnection is in direct contact with the metal pattern.Cited by (0)
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