Multichannel Metal Oxide Semiconductor (MOS) Transistors

Abstract

Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.

1 . A unit cell of a metal oxide semiconductor (MOS) transistor, comprising:
 an integrated circuit substrate;   a MOS transistor on the integrated circuit substrate, the MOS transistor having a vertical source region, a vertical drain region and a plurality of gates, the plurality of gates being between the vertical source region and the vertical drain region; and   a horizontal channel between the vertical source and drain regions, the horizontal channel including at least two spaced apart horizontal channel regions,   wherein widths of the plurality of gates contacted to the at least two horizontal channel regions are identical.   
   
   
       2 . The unit cell of  claim 1 , wherein the at least two spaced apart horizontal channel region comprise:
 an active region on the integrated circuit substrate; and   at least one epitaxial pattern on the active region and spaced apart from the active region.   
   
   
       3 . The unit cell of  claim 2 , wherein the at least one epitaxial pattern comprises first and second epitaxial patterns, the second epitaxial pattern being on the first epitaxial pattern and spaced apart from the first epitaxial pattern, the unit cell further comprising:
 a mask pattern on the second epitaxial pattern.   
   
   
       4 . The unit cell of  claim 3 , wherein the second epitaxial pattern is directly connected to the mask pattern. 
   
   
       5 . The unit cell of  claim 1 , wherein the source and drain regions comprise vertical source and drain regions, the vertical source region being on a first side of the horizontal channel region and the vertical drain region being on a second side of the horizontal channel region and spaced apart from the vertical source region. 
   
   
       6 . The unit cell of  claim 5 , further comprising:
 a gate pattern on the horizontal channel and between the at least two spaced apart horizontal channel regions; and   a gate insulation layer between the gate pattern and the at least two spaced apart horizontal channel regions.   
   
   
       7 . The unit cell of  claim 3 , further comprising:
 a source electrode electrically coupled to the vertical source region;   a drain electrode electrically coupled to the vertical drain region; and   a first insulation pattern between the source and drain electrodes and the integrated circuit substrate and between the gate pattern and the integrated circuit substrate.   
   
   
       8 . The unit cell of  claim 7 , wherein the gate pattern extends between an upper channel region of the at least two spaced apart horizontal channel regions and the mask pattern. 
   
   
       9 . The unit cell of  claim 8 , further comprising:
 a second insulation pattern on the horizontal channel and the vertical source and drain regions, wherein the second insulation pattern defines a gate opening on the horizontal channel, wherein the gate pattern is provided in the gate opening and wherein the source and drain electrodes extend through the second insulation pattern and are connected to the vertical source drain regions.   
   
   
       10 . The unit cell of  claim 9 , further comprising:
 a third insulation pattern on the second insulation pattern and the gate pattern, wherein the source and drain electrodes extend through the third insulation pattern and the second insulation pattern and are connected to the vertical source and drain regions.   
   
   
       11 . The unit cell of  claim 10 , wherein an upper surface of the first insulation pattern is higher relative to a lower surface of the gate pattern. 
   
   
       12 . A unit cell of a metal oxide semiconductor (MOS) transistor, comprising:
 an integrated circuit substrate including a trench and an active region higher than the trench, the active region protruding from the integrated circuit substrate to function as a horizontal channel;   the horizontal channel between a vertical source region and a vertical drain region, the horizontal channel including at least two single crystalline horizontal channel regions formed in spaced apart patterns, and further including the active region higher than the trench;   a plurality of gates between at least two single crystalline horizontal channel regions, wherein widths of the plurality of gates that contact the at least two single crystalline horizontal channel regions are substantially identical;   the vertical source region and the vertical drain region in other patterns at one side of the spaced apart patterns, respectively, wherein the vertical source and drain regions extend along sides of the at least two horizontal channel regions and sides of the active region protruding from the integrated circuit substrate; and   a vertical source electrode contacted to a side of the vertical source region and a vertical drain electrode contacted to a side of the vertical drain region.   
   
   
       13 . A transistor comprising:
 an integrated circuit substrate including a trench region to define an active region and a device insulation layer on a floor of the trench region;   a horizontal channel including a plurality of spaced apart channel layers on the active region, wherein widths of the plurality of spaced apart channel layers are substantially identical;   a gate pattern on the horizontal channel, the gate pattern including a plurality of gates simultaneously formed between the plurality of spaced apart channel layers;   a pair of junctions including a vertical source region and a vertical drain region on the device isolation layer; and   a vertical source electrode and a vertical drain electrode on the device isolation layer, the vertical source electrode contacting to a side of the source region and the vertical drain electrode contacting to a side of the drain region.   
   
   
       14 . The transistor of  claim 13 , wherein an upper surface of the device isolation layer is lower relative to the active region. 
   
   
       15 . The transistor of  claim 13 , wherein the pair of junction covers sides of the active region and sides of the plurality of spaced apart channel layers. 
   
   
       16 . The transistor of  claim 13 , wherein the plurality of spaced apart channel layers are single crystalline. 
   
   
       17 . The transistor of  claim 13 , wherein the horizontal channel comprises at least one gap region, in which at least one gate is formed, between the plurality of spaced apart channel layers.