PCI Express System and Method of Transiting Link State Thereof

Abstract

A PCI Express system and a method of transitioning link state thereof. The PCI Express system includes an upstream component, a downstream component and a link. The upstream component and the downstream component transmit data to each other via the link. When at least one of the upstream component and the downstream component stops data transmission under a normal working state and if the system idle time period reaches a threshold idle time, then transiting the link into a second link state

1 . A data transmission system, comprising:
 an upstream device;   at least one downstream device; and   a link, connected between the upstream device and the downstream device, wherein the link is in a first link state;   wherein when the upstream device outputs a turn-off signal to the downstream device, a time period is counted, if the upstream device does not receive an acknowledging signal from the downstream device to response the turn-off signal within the time period, the link is then transited from the first link state to a second link state to remove power of the link;   wherein the time period is set to be programmable so that the system has a reasonable time to power down.   
   
   
       2 . The data transmission system according to  claim 1 , wherein when the upstream device receives the acknowledging signal within the time period, the link is then transited from the first link state to the second link state according to the acknowledging signal. 
   
   
       3 . The data transmission system according to  claim 1 , the upstream device and the downstream device normally transmit data via the link when in the first link state. 
   
   
       4 . The data transmission system according to  claim 1 , wherein if the downstream device does not receive the turn-off signal within the time period, the link is then transited from the first link state to the second link state. 
   
   
       5 . The data transmission system according to  claim 1 , wherein the first link state is L 0  state. 
   
   
       6 . The data transmission system according to  claim 1 , wherein the second link state is L 2  state or L 3  state. 
   
   
       7 . The data transmission system according to  claim 1 , wherein the upstream device comprises a register for storing at least one time period. 
   
   
       8 . The data transmission system according to  claim 1 , wherein the upstream device comprises a timer for counting the time period. 
   
   
       9 . The data transmission system according to  claim 1 , wherein the system is a peripheral component interconnect express (PCIE) data transmission system. 
   
   
       10 . A method for managing link state of a data transmission system, the data transmission system comprising an upstream device, a downstream device and a link, the downstream device and the upstream device transmitting data via the link, the method comprising:
 sending out a turn-off signal to the downstream device and counting a time period, wherein the time period is set to be programmable so that the system has a reasonable time to power down; and   transiting the link from a first link state to a second link state to remove power of the link when a acknowledging signal is not received within the time period.   
   
   
       11 . The method according to  claim 10 , wherein the method further comprises outputting the acknowledging signal to the upstream device when receiving the turn-off signal. 
   
   
       12 . The method according to  claim 10 , wherein the method further comprises when the upstream device receives the acknowledging signal within the time period, transiting the link from the first link state to the second link state to remove the power of the link according to the acknowledging signal. 
   
   
       13 . The method according to  claim 10 , wherein the method further comprises transiting the link from the first link state to the second link state if the turn-off signal is not received within the time period. 
   
   
       14 . The method according to  claim 10 , wherein data is normally transmitted via the link when in the first link state. 
   
   
       15 . The method according to  claim 10 , wherein the first link state is L 0  state. 
   
   
       16 . The method according to  claim 10 , wherein the second link state is L 2  state or L 3  state. 
   
   
       17 . The method according to  claim 10 , wherein the method is applied to a peripheral component interconnect express (PCIE) data transmission system.