Thin film transistor substrate and method of manufacturing the same

Abstract

A thin film transistor (TFT) substrate having an improved wire structure without an under-cut phenomenon that may occur during formation of a gate wire having a double-layered structure and a method of manufacturing the same are provided, where the method includes forming a first metal layer made of at least one low resistance material selected from the group consisting of Al, AlNd, Cu, and Ag, forming a second metal layer made of at least one heat-resistant, etch-resistant material selected from the group consisting of Cr, CrNx, Ti, Mo, and MoW on the first metal layer, forming an etch mask on the second metal layer, sequentially etching the second metal layer and the first metal layer using the etch mask, and forming a second metal layer pattern and a first metal layer pattern, respectively, and selectively re-etching the second metal layer pattern using the etch mask to make a width of the second metal layer pattern smaller than or substantially equal to a width of the first metal layer pattern, and completing a gate wire.

1 . A thin film transistor (TFT) substrate comprising:
 a plurality of wires formed on an insulating substrate, the plurality of wires each including a first metal layer pattern made of at least one low resistance material selected from the group consisting of aluminum (Al), aluminum neodymium (AlNd), copper (Cu), and silver (Ag), a second metal layer pattern comprising chromium (Cr) on the first metal layer pattern, and a third metal layer pattern comprising chromium nitride (CrNx) on the second metal layer pattern,   wherein a width of the second metal layer pattern is smaller than or substantially equal to a width of the first metal layer pattern.   
   
   
       2 . The TFT substrate of  claim 1 , wherein the plurality wires are gate wires. 
   
   
       3 . The TFT substrate of  claim 2 , further comprising:
 a semiconductor pattern formed on the gate wires;   a plurality of data wires each including source/drain electrodes separately formed on the semiconductor pattern;   a TFT connected to the data wire and the gate wire;   a plurality of passivation layers each formed on the data wire; and   a plurality of pixel electrodes each formed at a pixel area defined by the gate wire and the data wire.   
   
   
       4 . The TFT substrate of  claim 1 , wherein a distance between a sidewall of the first metal layer pattern and a sidewall of the second metal layer pattern is equal to or less than 1 μm. 
   
   
       5 . The TFT substrate of  claim 1 , wherein the third metal layer pattern has a thickness of 200 Å or less. 
   
   
       6 . The TFT substrate of  claim 1 , wherein a width of the third metal layer pattern is smaller than or substantially equal to a width of the first metal layer pattern.