Variable sized aperture window of an analog-to-digital converter

Abstract

An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a multitude of inverter pairs interconnected in series, a specific permittivity material device, and a sequencer or multiplier. A second enhanced sampling system includes a variable sized aperture window, wherein a width of a sample pulse is narrowed through a variable clock mechanism to produce a faster sampling rate. This variable sized aperture window system can be used by itself, or in combination with any of the presently described multiple ADC distributed sampling systems.

1 . An analog-to-digital converter (ADC) circuit, comprising:
 a voltage controlled oscillator (VCO);   a counter;   a reference frequency source;   an input signal source; and   a logic gate.   
   
   
       2 . The circuit of  claim 1 , further comprising a connection to a central processing unit (CPU). 
   
   
       3 . The circuit of  claim 2 , wherein:
 an output of said VCO goes into said counter.   
   
   
       4 . The circuit of  claim 3 , wherein:
 said output is compared to said reference frequency through said gate.   
   
   
       5 . The circuit of  claim 2 , wherein:
 said CPU controls resets of said counter.   
   
   
       6 . The circuit of  claim 1 , wherein:
 said logic gate is an exclusive-OR (XOR) gate.   
   
   
       7 . A computer array, comprising:
 a substrate;   an input signal source;   a first analog-to-digital converter circuit integrated on said substrate and coupled to said input signal source, said first analog-to-digital converter circuit including
 a VCO, 
 a counter, 
 a reference frequency source; and 
 a logic gate; 
   a first computer integrated on said substrate, said first computer being coupled to said first analog-to-digital converter circuit; and   a second computer integrated on said substrate.   
   
   
       8 . The computer array of  claim 7 , further comprising:
 a second analog-to-digital converter circuit integrated on said substrate and coupled to said input signal source and to said second computer, said second analog-to-digital converter circuit including
 a VCO, 
 a counter, 
 a reference frequency source, 
 a logic gate. 
   
   
   
       9 . The computer array of  claim 8 , further comprising:
 a sampling clock signal source operative to provide a clock signal; and   a first time distribution apparatus coupled to said sampling clock signal source; and   wherein said first analog-to-digital converter circuit is coupled to said first time distribution apparatus.   
   
   
       10 . The computer array of  claim 9 , wherein said second analog-to-digital converter circuit is coupled to said first time distribution apparatus. 
   
   
       11 . The computer array of  claim 9 , wherein said second analog-to-digital converter circuit is coupled to said time distribution apparatus, said time distribution apparatus being operative to increase the time it takes for said clock signal to reach said second analog-to-digital converter circuit with respect to the time it takes for said clock signal to reach said first analog to digital converter. 
   
   
       12 . The computer array of  claim 8 , further comprising a data path connecting said first computer to said second computer. 
   
   
       13 . The computer array of  claim 8 , further comprising:
 a third computer integrated on said circuit substrate;   a fourth computer integrated on said circuit substrate; and   a data path connection said third computer to said fourth computer.   
   
   
       14 . The computer array of  claim 7 , wherein said logic gate is an exclusive-OR (XOR) gate. 
   
   
       15 . The computer array of  claim 7 , wherein said VCO is operative to provide an output signal to said counter 
   
   
       16 . The computer array of  claim 15 , wherein said logic gate is operative to compare said output signal of said VCO with a reference frequency provided by said reference frequency source. 
   
   
       17 . The computer array of  claim 7 , wherein said first computer is operative to control said counter. 
   
   
       18 . The computer array of  claim 7 , wherein:
 said VCO includes an input and an output;   said input of said VCO is coupled to said input signal source; and   said output of said VCO is coupled to said counter.   
   
   
       19 . The computer array of  claim 7 , further comprising a second analog-to-digital converter circuit coupled to said input signal source and said second computer, said second analog-to-digital converter circuit including:
 an input sampling switch;   a sample and hold capacitor;   a variable aperture clock;   a counter; and   a VCO.