Mips recovery technique

Abstract

Self-calibration of devices such as computer and graphics processors permits adjustment of processor clock rates, and access to normally unused processor capacity. Processor clock rates specified by device manufacturers are normally selected to insure operation across the entire manufacturer-specified range of operating temperatures and supply voltages. By limiting processor clock rates to nominal values, even when operating well within manufacturer-specified temperature and/or supply voltage limits, designers sacrifice processor capacity. By determining the upper limits of processor clock rates at which reliable operation can be realized, and adjusting processor clock rates to match those speeds, a representative embodiment of the present invention permits device users to gain additional, previously inaccessible processing capacity.

1 - 30 . (canceled) 
     
     
         31 . An electronic device comprising:
 a processor circuit operating at a processor clock rate determined by a programmable clock source under control of the processor circuit, the processor circuit communicatively coupled to a non-volatile memory and to a real time clock circuit for determining elapsed time,   wherein the processor circuit is arranged to:
 set an initial processor clock rate upon power-up of the processor circuit, using contents of the non-volatile memory; 
 detect processor circuit operational errors during operation of the electronic device for its intended use; and 
 automatically adjust the processor clock rate during operation of the electronic device for its intended use, according to a measurement of a time interval free of processor circuit operational errors. 
   
     
     
         32 . The device of  claim 31  further comprising:
 a temperature sensing circuit communicatively coupled to the processor circuit.   
     
     
         33 . The device of  claim 31  wherein setting the initial processor clock rate comprises testing a range of clock rates to determine a maximum reliable processor clock rate. 
     
     
         34 . The device of  claim 33  wherein the maximum reliable processor clock rate is stored in the non-volatile memory. 
     
     
         35 . The device of  claim 31  wherein setting the initial processor clock rate comprises retrieving a processor clock rate from the non-volatile memory. 
     
     
         36 . The device of  claim 35  wherein the initial processor clock rate is set to a nominal clock rate, if the retrieved processor clock rate is invalid. 
     
     
         37 . The device of  claim 31  wherein the non-volatile memory comprises temperature related operating characteristics of the processor circuit. 
     
     
         38 . The device of  claim 37  wherein the temperature related operating characteristics of the processor circuit are determined during manufacture of the processor circuit. 
     
     
         39 . The device of  claim 31  wherein adjusting the processor clock rate comprises increasing the processor clock rate, if the measurement of the time interval free of processor circuit operational errors is above a first threshold, and decreasing the processor clock rate, if the measurement of the time interval free of processor circuit operational errors is below a second threshold. 
     
     
         40 . The device of  claim 31  wherein the adjusted processor clock rate is stored in the non-volatile memory. 
     
     
         41 . The device of  claim 31  wherein the programmable clock source is disposed on the same integrated circuit as the processor circuit. 
     
     
         42 . The device of  claim 31  wherein the non-volatile memory is disposed on the same integrated circuit as the processor circuit. 
     
     
         43 . The device of  claim 31  wherein the programmable clock source and the non-volatile memory are disposed on the same integrate circuit as the processor circuit. 
     
     
         44 . The device of  claim 31  wherein the processor circuit comprises a microprocessor core. 
     
     
         45 . The device of  claim 31  wherein the processor circuit comprises a digital signal processor core.