Semiconductor Devices and Methods of Manufacture Thereof

Abstract

Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.

1 . A method of manufacturing a semiconductor device, the method comprising:
 forming a first multiple gate transistor comprising a PMOS transistor, the first multiple gate transistor comprising a first gate dielectric material and first gate electrodes proximate the first gate dielectric material, wherein the first gate electrodes are doped n-type by implanting a n-type dopant; and   forming a second multiple gate transistor comprising a NMOS transistor proximate the first multiple gate transistor, the second multiple gate transistor comprising a second gate dielectric material and second gate electrodes proximate the second gate dielectric material, wherein the second gate dielectric material is different than the first gate dielectric material, and wherein either the first gate dielectric material, the second gate dielectric material, or both the first gate dielectric material and the second gate dielectric material have a dielectric constant of about 4.0 or greater.   
   
   
       2 . The method according to  claim 1 , wherein either the first gate dielectric material, the second gate dielectric material, or both the first gate dielectric material and the second gate dielectric material comprise a Fermi-pinning material. 
   
   
       3 . The method according to  claim 2 , wherein the Fermi-pinning material comprises Hf, La, Al, Y, Sc, Lu, Lr, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Zr, Yb, or combinations thereof. 
   
   
       4 . The method according to  claim 1 , wherein the first multiple gate transistor comprises a plurality of gate electrodes proximate the first gate dielectric material, further comprising implanting a Fermi-pinning material into at least the plurality of gate electrodes. 
   
   
       5 . The method according to  claim 1 , wherein forming the first multiple gate transistor and forming the second multiple gate transistor comprise forming a plurality of fin structures, depositing a single layer of gate dielectric material over the plurality of fin structures, and implanting a Fermi-pinning material into the single layer of gate dielectric material of the first multiple gate transistor, but not into the single layer of gave dielectric material of the second multiple gate transistor. 
   
   
       6 . The method according to  claim 1 , wherein the first multiple gate transistor comprises a plurality of first gates proximate the first gate dielectric material, further comprising a first thin layer of silicon disposed between the first gate dielectric material and the plurality of first gates; and wherein the second multiple gate transistor comprises a plurality of second gates proximate the second gate dielectric material, further comprising a second thin layer of silicon disposed between the second gate dielectric material and the plurality of second gates. 
   
   
       7 . The method according to  claim 1 , wherein implanting a n-type dopant comprises implanting As, P, Sb, or Bi. 
   
   
       8 . The method according to  claim 1 , wherein the second gate electrodes are doped p-type by implanting a p-type dopant, 
   
   
       9 . The method according to  claim 8 , wherein implanting a p-type dopant comprises implanting B, Al, Ga, In, or Tl. 
   
   
       10 . A method of manufacturing a semiconductor device, the method comprising:
 forming a PMOS transistor, the PMOS transistor including at least two first gate electrodes, a first gate dielectric being disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first gate dielectric material, wherein the at least two first gate electrodes are doped n-type by implanting a n-type dopant; and   forming a NMOS transistor proximate the PMOS transistor, the NMOS transistor including at least two second gate electrodes, a second gate dielectric being disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second gate dielectric material, wherein the second gate dielectric material is different than the first gate dielectric material.   
   
   
       11 . The method according to  claim 10 , further comprising forming a third material over the first material of the NMOS transistor, wherein the first material and the second material comprise the first gate dielectric material of the PMOS transistor, and wherein the first material and the third material comprise the second gate dielectric material of the NMOS transistor. 
   
   
       12 . The method according to  claim 10 , wherein forming the PMOS transistor and forming the NMOS transistor comprise forming at least one fin structure, the at least one fin structure comprising channels of the PMOS transistor and the NMOS transistor, further comprising forming a first material over the at least one structure, forming a second material over the first material, removing the second material and the first material from over the at least one fin structure of the NMOS transistor, and forming a third material over the at least one fin structure of the NMOS transistor, wherein the first material and the second material comprise the first gate dielectric material of the PMOS transistor, and wherein the third material comprises the second gate dielectric material of the NMOS transistor. 
   
   
       13 . The method according to  claim 10 , wherein forming the PMOS transistor and forming the NMOS transistor comprise forming at least one fin structure, the at least one fin structure comprising channels of the PMOS transistor and the NMOS transistor, further comprising forming a first material over the at least one fin structure, forming a second material over the first material, forming a first gate material over the second material, removing the first gate material and the second material from over the at least one fin structure of the NMOS transistor, forming a third material over the first material of the NMOS transistor, and forming a second gate material over the third material of the NMOS transistor, wherein the first material and the second material comprise the first gate dielectric material of the PMOS transistor, wherein the first material and the third material comprise the second gate dielectric material of the NMOS transistor, wherein the at least two first gate electrodes of the PMOS transistor comprise the first gate material, and wherein the at least two second gate electrodes of the NMOS transistor comprise the second gate material. 
   
   
       14 . The method according to  claim 10 , wherein forming the PMOS transistor and forming the NMOS transistor comprise forming at least one fin structure, the at least one fin structure comprising channels of the PMOS transistor and the NMOS transistor, further comprising forming a first material over the at least one fin structure, forming a second material over the first material, forming a first gate material over the second material, removing the first gate material, the second material, and the first material from over the at least one fin structure of the NMOS transistor, forming a third material over the at least one fin structure of the NMOS transistor, and forming a second gate material over the third material of the NMOS transistor, wherein the first material and the second material comprise the first gate dielectric material of the PMOS transistor, wherein the third material comprises the second gate dielectric material of the NMOS transistor, wherein the at least two first gate electrodes of the PMOS transistor comprise the first gate material, and wherein the at least two second gate electrodes of the NMOS transistor comprise the second gate material. 
   
   
       15 . The method according to  claim 10 , wherein forming the PMOS transistor and forming the NMOS transistor comprise forming a plurality of fin structures, the plurality of fin structures comprising channels of the PMOS transistor and the NMOS transistor, further comprising forming a first material over the plurality of fin structures, forming a first gate material over the first material, removing the first gate material and the first material from over the NMOS transistor, forming a second material over the fin structure of the NMOS transistor, and forming a second gate material over the second material, wherein the first material comprises the first gate dielectric material of the PMOS transistor, wherein the second material comprises the second gate dielectric material of the NMOS transistor, wherein the at least two first gate electrodes of the PMOS transistor comprise the first gate material, and wherein the at least two second gate electrodes of the NMOS transistor comprise the second gate material. 
   
   
       16 . The method according to  claim 10 , further comprising, before forming the PMOS transistor and forming the NMOS transistor:
 providing a workpiece, the workpiece comprising a silicon-on-insulator (SOI) substrate having a substrate, a buried insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the buried insulating layer, the workpiece comprising a first region and a second region;   forming at least one first fin structure within the layer of semiconductor material in the first region, the at least one first fin structure comprising a first sidewall and an opposing second sidewall;   forming at least one second fin structure within the layer of semiconductor material in the second region, the at least one second fin structure comprising a first sidewall and an opposing second sidewall;   forming the first gate dielectric material over at least the first and second sidewalls of the at least one first fin structure; and   forming the second gate dielectric material over at least the first and second sidewalls of the at least one second fin structure.   
   
   
       17 . The method according to  claim 16 , further comprising:
 forming the at least two first gate electrodes over the first gate dielectric material;   forming the at least two second gate electrodes over the second gate dielectric material; and   treating the first gate dielectric material and the second gate dielectric material with a silicon-containing substance before forming the at least two first gate electrodes over the first gate dielectric material and before forming the at least two second gate electrodes over the second gate dielectric material.   
   
   
       18 . The method according to  claim 10 , wherein implanting a n-type dopant comprises implanting As, P, Sb, or Bi. 
   
   
       19 . The method according to  claim 10 , wherein the at least two second gate electrodes are doped p-type by implanting a p-type dopant. 
   
   
       20 . The method according to  claim 19 , wherein implanting a p-type dopant comprises implanting B, Al, Ga, In, or Tl.