Methods of forming wiring to transistor and related transistor

Abstract

Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.

1 . A transistor comprising:
 a gate;   a source/drain region;   a channel adjacent to the gate; and   a contact to at least one of the source/drain region and the gate that extends from a channel side of the transistor.   
   
   
       2 . The transistor of  claim 1 , further comprising a first dielectric stress layer applied adjacent to the gate and a second dielectric stress layer applied adjacent to the channel. 
   
   
       3 . The transistor of  claim 1 , further comprising a contact to at least one of the source, drain and gate regions that extends from a gate side of the transistor. 
   
   
       4 . The transistor of  claim 1 , each of the gate, the source/drain region and the channel being formed on a semiconductor-on insulator (SOI) substrate using masks that are mirror images of an intended layout. 
   
   
       5 . The transistor of  claim 4 , wherein the SOI substrate includes a SOI layer, a buried insulator layer and a silicon substrate. 
   
   
       6 . The transistor of  claim 1 , further comprising a wiring to the contact on the channel side of the transistor. 
   
   
       7 . The transistor of  claim 1 , further comprising an isolation region on the a channel side of the transistor.