Method and System for Addressing a Plurality of Ethernet Controllers Integrated into a Single Chip Which Utilizes a Single Bus Interface

Abstract

A system for arbitrating access to a shared resource is disclosed and may include a bus interface, a first network controller for handling a first host function associated with a first host process, a second network controller for handling a second host function associated with a second host process, and an arbitrator for granting access to the shared resource for one of the first host process and the second host process. The arbitrator may facilitate a transfer of information to and from the bus interface and the shared resource. The first network controller and the second network controller may be integrated within a single chip. The shared resource may be a nonvolatile memory, flash memory interface, an EEPROM interface, and/or a Serial Programming Interface (SPI).

1 - 42 . (canceled) 
   
   
       43 . A system for arbitrating access to a shared resource, comprising:
 a bus interface;   a first network controller for handling a first host function associated with a first host process;   a second network controller for handling a second host function associated with a second host process; and   an arbitrator for granting access to the shared resource for one of the first host process and the second host process, and facilitating a transfer of information to and from the bus interface and the shared resource,   wherein the first network controller and the second network controller are integrated within a single chip.   
   
   
       44 . The system of  claim 43 , wherein the shared resource is a nonvolatile memory. 
   
   
       45 . The system of  claim 43 , wherein the shared resource is a flash memory interface. 
   
   
       46 . The system of  claim 43 , wherein the shared resource is an EEPROM interface. 
   
   
       47 . The system of  claim 43 , wherein the shared resource is a Serial Programming Interface (SPI). 
   
   
       48 . The system of  claim 43 , wherein the shared resource is a System Management Bus (SMBus). 
   
   
       49 . The system of  claim 43 , wherein the shared resource is a general purpose input/output (GPIO) interface. 
   
   
       50 . The system of  claim 43 , wherein the bus interface is a PCI. 
   
   
       51 . The system of  claim 43 , wherein the bus interface is a PCI-X. 
   
   
       52 . The system of  claim 43 , wherein the bus interface is a PCI variant. 
   
   
       53 . The system of  claim 43 , wherein one or both of the first and second network controllers are Ethernet controllers. 
   
   
       54 . The system of  claim 43 , wherein one or both of the first and second network controllers are Fibre channel controllers. 
   
   
       55 . The system of  claim 43 , wherein the first and second host processes are PCI processes. 
   
   
       56 . The system of  claim 43 , wherein the first and second host functions are PCI functions. 
   
   
       57 . The system of  claim 43 , wherein status on the bus interface is provided by registers. 
   
   
       59 . The system of  claim 43 , wherein control of the bus interface is provided by registers. 
   
   
       60 . A method of arbitrating access to a shared resource, comprising:
 receiving a request to access the shared resource from a first requester;   receiving a request to access the shared resource from a second requester;   granting access to the shared resource to the first requester;   denying access to the shared resource to a second requester; and   facilitating a transfer of information, according to the first requester, to and from a bus interface and the shared resource.   
   
   
       61 . The method of  claim 59 , wherein the shared resource is a nonvolatile memory. 
   
   
       62 . The method of  claim 59 , wherein the shared resource is a flash memory interface. 
   
   
       63 . The method of  claim 59 , wherein the shared resource is an EEPROM interface. 
   
   
       64 . The method of  claim 59 , wherein the shared resource is a Serial Programming Interface (SPI). 
   
   
       65 . The method of  claim 59 , wherein the shared resource is a System Management Bus (SMBus). 
   
   
       66 . The method of  claim 59 , wherein the shared resource is a general purpose input/output (GPIO) interface. 
   
   
       67 . The method of  claim 59 , wherein the bus interface is a PCI. 
   
   
       68 . The method of  claim 59 , wherein the bus interface is a PCI-X. 
   
   
       69 . The method of  claim 59 , wherein the bus interface is a PCI variant. 
   
   
       70 . The method of  claim 59 , wherein the first and second requesters are PCI processes. 
   
   
       71 . The method of  claim 59 , wherein status on the bus interface is provided by registers. 
   
   
       72 . The method of  claim 59 , wherein control of the bus interface is provided by registers.