Majority voter circuits and semiconductor device including the same

Abstract

A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

1 . A majority voter circuit, comprising:
 an input circuit connected between a first node, a second node and a common node and receiving data of odd-number bits and inverted data of odd-number bits respectively excluding a predetermined-number bit from data of plural bits and inverted data of plural bits to generate a voltage difference between the first node and the second node; and   an amplifying circuit connected to a first power source and between the first node and between the second node, and detecting and amplifying the voltage difference between the first node and the second node,   wherein the majority voter circuit determines a majority by comparing the number of bits having a value of “0” and the number of bits having a value of “1” to output a selecting signal.   
   
   
       2 . The majority voter circuit of  claim 1 , wherein the input circuit excludes the same bit respectively from the data and the inverted data. 
   
   
       3 . The majority voter circuit of  claim 2 , wherein the input circuit comprises
 a data input circuit having a plurality of first NMOS transistors which respectively have a drain connected to the first node, a source connected to the common node and a gate receiving the data of the odd-number bits; and   an inverted data input circuit including a plurality of second NMOS transistors which respectively have a drain connected to the second node, a source connected to the common node and a gate receiving the inverted data of the odd-number bits.   
   
   
       4 . The majority voter circuit of  claim 1 , wherein the amplifying circuit comprises
 a first PMOS transistor having a drain and a gate which are connected to the first node and a source connected to the first power source; and   a second PMOS transistor having a drain connected to the second node, a gate connected to the first node and a source connected to the first power source.   
   
   
       5 . The majority voter circuit of  claim 1 , further comprising, a third NMOS transistor connected between the common node and a second power source and activating the majority voter circuit in response to an enable signal applied from an external circuit. 
   
   
       6 . A data bus inversion circuit, comprising:
 a majority voter circuit receiving data of plural bits and inverted data of plural bits and comparing the number of bits having a value of “0” and the number of bits having a value of “1” respectively in data of odd-number bits and inverted data of odd-number bits respectively excluding a predetermined-number bit from the data of plural bits and the inverted data of plural bits to determine a majority and to output a selecting signal; and   an encoder receiving the data and the inverted data and selecting either of the data and the inverted data to output low weight coding data in response to the selecting signal.   
   
   
       7 . The data bus inversion circuit of  claim 6 , wherein the majority voter circuit comprises
 an input circuit connected between a first node, a second node and a common node and receiving the data of odd-number bits and the inverted data of odd-number bits respectively excluding a predetermined-number bit from the data of plural bits and the inverted data of plural bits to generate a voltage difference between the first node and the second node; and   an amplifying circuit connected to a first power source and between the first node and between the second node, and detecting and amplifying the voltage difference between the first node and the second node,   wherein the majority voter circuit determines a majority by comparing the number of bits having a value of “0” and the number of bits having a value of “1” to output a selecting signal.   
   
   
       8 . The data bus inversion circuit of  claim 7 , wherein the input circuit excludes the same bit respectively from the data and the inverted data. 
   
   
       9 . The data bus inversion circuit of  claim 8 , wherein the input circuit comprises
 a data input circuit having a plurality of first NMOS transistors which respectively have a drain connected to the first node, a source connected to the common node and a gate receiving the data of the odd-number bits; and   an inverted data input circuit including a plurality of second NMOS transistors which respectively have a drain connected to the second node, a source connected to the common node and a gate receiving the inverted data of the odd-number bits.   
   
   
       10 . The data bus inversion circuit of  claim 7 , wherein the amplifying circuit comprises
 a first PMOS transistor having a drain and a gate which are connected to the first node and a source connected to the first power source; and   a second PMOS transistor having a drain connected to the second node, a gate connected to the first node and a source connected to the first power source.   
   
   
       11 . A semiconductor circuit, comprising:
 a data generating circuit for generating data of plural bits and inverted data of plural bits; and   a data bus inversion circuit receiving the data of plural bits and the inverted data of plural bits, comparing the number of bits having a value of “0” and the number of bits having a value of “1” respectively in data of odd-number bits and inverted data of odd-number bits respectively excluding a predetermined-number bit from the data of plural bits and the inverted data of plural bits to determine a majority and to output a selecting signal and selecting either of the data and the inverted data to output low weight coding data together with the selecting signal.   
   
   
       12 . The semiconductor circuit of  claim 11 , wherein the data bus inversion circuit comprises,
 a majority voter circuit receiving the data of plural bits and the inverted data of plural bits and comparing the number of bits having a value of “0” and the number of bits having a value of “1” respectively in data of odd-number bits and inverted data of odd-number bits respectively excluding a predetermined-number bit from the data of plural bits and the inverted data of plural bits to determine a majority and to output the selecting signal; and   an encoder receiving the data and the inverted data and selecting either of the data and the inverted data to output the low weight coding data in response to the selecting signal.   
   
   
       13 . The semiconductor circuit of  claim 11 , further comprising, a data output circuit receiving the selecting signal and the low weight coding data and outputting the selecting signal and the low weight coding data to an external circuit.