Media Action Script Acceleration Apparatus, System and Method

Abstract

Exemplary apparatus, method, and system embodiments provide for processing an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; first circuitry configured to convert a plurality of descriptive elements of the action script into a plurality of operational codes; and second circuitry configured to execute the plurality of operational codes using corresponding data stored in the first memory to generate pixel data for the graphical image. Exemplary embodiments may further include third circuitry configured to parse the action script into the plurality of descriptive elements and the corresponding data, and fourth circuitry configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

1 . An apparatus for processing an action script for visual display of a graphical image, the apparatus comprising:
 a first memory;   first circuitry configured to convert a plurality of descriptive elements of the action script into a plurality of operational codes; and   second circuitry configured to perform an operation corresponding to an operational code of the plurality of operational codes using corresponding data stored in the first memory to generate pixel data for the graphical image.   
   
   
       2 . The apparatus of  claim 1 , further comprising:
 third circuitry configured to parse the action script into the plurality of descriptive elements and the corresponding data.   
   
   
       3 . The apparatus of  claim 2 , further comprising:
 fourth circuitry configured to decode a descriptive element to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script.   
   
   
       4 . The apparatus of  claim 2 , wherein the third circuitry further comprises:
 a decoder configured to determine a type of descriptive element;   a parsing controller coupled to the decoder and configured to determine or select a number of bits to parse parameter;   a stream register configured to store a plurality of bits of the action script; and   at least one barrel shifter configured to shift out of the stream register a number of bits designated by the number of bits to parse parameter.   
   
   
       5 . The apparatus of  claim 1 , further comprising:
 fifth circuitry configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.   
   
   
       6 . The apparatus of  claim 5 , wherein the first memory is further configured to store the plurality of operational codes and plurality of control words in a database structure. 
   
   
       7 . The apparatus of  claim 5 , wherein each control word of the plurality of control words comprises a starting or an ending x-coordinate and y-coordinate for a corresponding line or curve segment for the graphical image. 
   
   
       8 . The apparatus of  claim 7 , wherein each control word of the plurality of control words further comprises a control x-coordinate and control y-coordinate for a corresponding curve segment for the graphical image. 
   
   
       9 . The apparatus of  claim 5 , wherein each control word of the plurality of control words comprises a first memory address for line style array for a corresponding line or curve segment for the graphical image and a second memory address for fill style array for a plurality of line or curve segments comprising the graphical image. 
   
   
       10 . The apparatus of  claim 5 , wherein each control word of the plurality of control words comprises a line style array for a corresponding line or curve segment for the graphical image and a second memory address for fill style array for a plurality of line or curve segments comprising the graphical image. 
   
   
       11 . The apparatus of  claim 1 , further comprising:
 sixth circuitry configured to separate the action script from other data.   
   
   
       12 . The apparatus of  claim 1 , wherein the plurality of descriptive elements are a plurality of tags or bytecodes. 
   
   
       13 . The apparatus of  claim 1 , wherein the plurality of descriptive elements are a plurality of control tags, definition tags, and dictionary tags or dictionary repositories. 
   
   
       14 . The apparatus of  claim 1 , further comprising:
 a second memory storing the plurality of operational codes; and   wherein the first circuitry is further configured to convert the action script directly to the plurality of operational codes by performing a deterministic function on each descriptive element of the plurality of descriptive elements to generate a corresponding result and to use the result to determine a corresponding operational code of the plurality of operational codes.   
   
   
       15 . The apparatus of  claim 1 , further comprising:
 a second memory storing a look up table having the plurality of operational codes; and   wherein the first circuitry is further configured to convert the action script directly to the plurality of operational codes by performing a hash function on each descriptive element of the plurality of descriptive elements to generate a corresponding hash result and to use the hash result as an index or entry into the look up table to determine a corresponding operational code of the plurality of operational codes.   
   
   
       16 . The apparatus of  claim 1 , further comprising:
 seventh circuitry configured to decode each operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control the second circuitry to perform a selected operation, of a plurality of operations, corresponding to a selected operational code of the plurality of operational codes.   
   
   
       17 . The apparatus of  claim 16 , wherein the second circuitry further comprises a floating point circuit, and wherein the seventh circuitry is further configured to generate a first corresponding control signal to enable the floating point circuit to perform the selected operation. 
   
   
       18 . The apparatus of  claim 17 , wherein the seventh circuitry is further configured to generate a second corresponding control signal to select a floating point calculation result provided by the enabled floating point circuit. 
   
   
       19 . The apparatus of  claim 16 , wherein the second circuitry further comprises an arithmetic logic unit, and wherein the seventh circuitry is further configured to decode an operational code of the plurality of operational codes to generate a corresponding plurality of control signals to select a calculation result generated by the arithmetic logic unit. 
   
   
       20 . The apparatus of  claim 1 , wherein the second circuitry further comprises
 at least one arithmetic logic unit; and   at least one floating point circuit.   
   
   
       21 . The apparatus of  claim 20 , wherein the at least one arithmetic logic unit further comprises:
 an adder circuit;   a subtractor circuit;   a bitwise-OR logic circuit;   a bitwise-AND logic circuit;   a bitwise-exclusive OR logic circuit;   a barrel shifter circuit; and   an output multiplexer.   
   
   
       22 . The apparatus of  claim 20 , wherein the at least one floating point circuit further comprises:
 a floating point adder and subtractor circuit;   a floating point multiplier circuit;   a floating point divider circuit;   a floating point comparator circuit;   an integer-to-floating point converter circuit;   a floating point-to-integer converter circuit; and   an output multiplexer.   
   
   
       23 . The apparatus of  claim 22 , further comprising:
 a control circuit configured to control two floating point comparator circuits to perform a comparison and to use results of the comparisons to perform a conditional branch operation during a single clock cycle.   
   
   
       24 . The apparatus of  claim 22 , further comprising:
 a control circuit configured to control a plurality of floating point comparator circuits to perform at least four comparisons corresponding to four conditions and to use results of the comparisons to perform a conditional branch operation during a single clock cycle.   
   
   
       25 . The apparatus of  claim 20 , further comprising:
 a configurable interconnect coupled to the at least one arithmetic logic unit and to the at least one floating point execution unit, the configurable interconnect comprising:   a multiport register; and   a cross-point switch for configuration of a data path.   
   
   
       26 . The apparatus of  claim 1 , further comprising:
 eighth circuitry configured to match a plurality of line or curve segments of a boundary of the graphical image.   
   
   
       27 . The apparatus of  claim 26 , wherein the eighth circuitry is further configured to determine a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image. 
   
   
       28 . The apparatus of  claim 1 , further comprising:
 ninth circuitry configured to apply a fill style to generate pixel data for an area of the graphical image.   
   
   
       29 . The apparatus of  claim 28 , further comprising:
 tenth circuitry configured to apply a line style by forming a second graphical image from a boundary of the graphical image, and wherein the ninth circuitry is further configured to apply a fill style to the second graphical image to generate pixel data for the line style.   
   
   
       30 . The apparatus of  claim 1 , further comprising:
 eleventh circuitry configured to perform a Transmission Control Protocol (“TCP”) or Internet Protocol (“IP”) for reception of a data file.   
   
   
       31 . The apparatus of  claim 1 , further comprising:
 twelfth circuitry configured to perform hypertext transfer protocol (“HTTP”) for reception of a data file.   
   
   
       32 . The apparatus of  claim 31 , further comprising:
 thirteenth circuitry configured to pre-fetch referenced data of the data file.   
   
   
       33 . The apparatus of  claim 31 , further comprising:
 fourteenth circuitry configured to generate pixel data for hypertext markup language (“HTML”) or extensible markup language (“XML”) data of the data file.   
   
   
       34 . The apparatus of  claim 33 , further comprising:
 a frame buffer;   wherein the second circuitry is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the fourteenth circuitry is further configured to transfer the pixel data for the HTML or XML data to the frame buffer.   
   
   
       35 . The apparatus of  claim 33 , further comprising:
 a frame buffer; and   a visual display;   wherein the second circuitry is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the fourteenth circuitry is further configured to transfer the pixel data for the HTML or XML data to the visual display.   
   
   
       36 . The apparatus of  claim 33 , further comprising:
 a frame buffer; and   a display controller;   wherein the second circuitry is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the fourteenth circuitry is further configured to transfer the pixel data for the HTML or XML data to the display controller.   
   
   
       37 . The apparatus of  claim 33 , further comprising:
 a display controller;   wherein the second circuitry is further configured to transfer the pixel data for the graphical image to the display controller and wherein the fourteenth circuitry is further configured to transfer the pixel data for the HTML or XML data to the display controller.   
   
   
       38 . The apparatus of  claim 37 , wherein the second circuitry further comprises a frame buffer memory circuit. 
   
   
       39 . The apparatus of  claim 1 , wherein the first circuitry and the second circuitry are embodied in a single integrated circuit. 
   
   
       40 . The apparatus of  claim 1 , wherein the first circuitry and the second circuitry further comprise a plurality of processor cores. 
   
   
       41 . The apparatus of  claim 1 , wherein the plurality of descriptive elements are a specification of at least one graphical image in a form which at least partially is not pixel-by-pixel. 
   
   
       42 . The apparatus of  claim 1 , wherein the plurality of descriptive elements are a specification of at least one graphical image in a form which at least partially is not a pixel bitmap or a pixel matrix. 
   
   
       43 . The apparatus of  claim 1 , wherein each operational code of the plurality of operational codes is a hardware-level instruction. 
   
   
       44 . The apparatus of  claim 1 , wherein the second circuitry further comprises a hardware decoder configured to decode a selected operational code of the plurality of operational codes into a plurality of hardware-level microcode, or hardware-level binary instructions, or hardware-level control signals. 
   
   
       45 . The apparatus of  claim 1 , wherein the action script is a data file which has not been fully compiled to machine code and which comprises at least one descriptive element specifying the graphical image at least partially in a non-pixel-by-pixel form. 
   
   
       46 . The apparatus of  claim 1 , wherein the action script is a data file specifying the graphical image at least partially in a non-pixel-by-pixel form and which comprises an ASCII-encoded scripting language or bytecode. 
   
   
       47 . The apparatus of  claim 1 , wherein the graphical image is an image of any kind for visual display which has been specified at least partially in a non-pixel-by-pixel form in the action script. 
   
   
       48 . An apparatus for processing an action script for visual display of a graphical image, the apparatus comprising:
 a first memory circuit;   a parser circuit to parse the action script into a plurality of descriptive elements and corresponding data;   a converter circuit to convert the plurality of descriptive elements of the action script into a plurality of operational codes; and   an execution circuit to perform a selected operation in response to a selected operational code of the plurality of operational codes using corresponding data stored in the first memory circuit to generate pixel data for the graphical image.   
   
   
       49 . The apparatus of  claim 48 , further comprising:
 a decoder circuit to decode a descriptive element to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script by the parser circuit.   
   
   
       50 . The apparatus of  claim 49 , wherein the decoder circuit further comprises:
 a decoder to determine a type of descriptive element;   and wherein the parser circuit further comprises:   a parsing controller to determine or select a number of bits to parse parameter;   a stream register to store a plurality of bits of the action script; and   at least one barrel shifter to shift out of the stream register a number of bits designated by the number of bits to parse parameter.   
   
   
       51 . The apparatus of  claim 48 , wherein the parser circuit is further configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields. 
   
   
       52 . The apparatus of  claim 51 , wherein the first memory is further configured to store the plurality of operational codes and plurality of control words in a database structure. 
   
   
       53 . The apparatus of  claim 48 , wherein the plurality of descriptive elements are a plurality of tags or bytecodes. 
   
   
       54 . The apparatus of  claim 48 , further comprising:
 a second memory storing a look up table having the plurality of operational codes; and   wherein the converter circuit is further configured to perform a hash function on each descriptive element of the plurality of descriptive elements to generate a corresponding hash result and to use the hash result as an index or entry into the look up table to determine a corresponding operational code of the plurality of operational codes.   
   
   
       55 . The apparatus of  claim 48 , further comprising:
 a decoder circuit to decode each operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control the execution circuit to perform the selected operation, of a plurality of operations, corresponding to the selected operational code of the plurality of operational codes.   
   
   
       56 . The apparatus of  claim 48 , wherein the execution circuit further comprises
 at least one arithmetic logic unit; and   at least one floating point circuit.   
   
   
       57 . The apparatus of  claim 56 , wherein the at least one arithmetic logic unit further comprises:
 an adder circuit;   a subtractor circuit;   a bitwise-OR logic circuit;   a bitwise-AND logic circuit;   a bitwise-exclusive OR logic circuit;   at least one barrel shifter circuit; and   an output multiplexer.   
   
   
       58 . The apparatus of  claim 56 , wherein the at least one floating point circuit further comprises:
 a floating point adder and subtractor circuit;   a floating point multiplier circuit;   a floating point divider circuit;   a floating point comparator circuit;   an integer-to-floating point converter circuit;   a floating point-to-integer converter circuit; and   an output multiplexer.   
   
   
       59 . The apparatus of  claim 58 , further comprising:
 a control circuit to control a plurality of floating point comparator circuits to perform at least four comparisons corresponding to four conditions and to use results of the comparisons to perform a conditional branch operation during a single clock cycle.   
   
   
       60 . The apparatus of  claim 56 , further comprising:
 a configurable interconnect coupled to the at least one arithmetic logic unit and to the at least one floating point execution unit, the configurable interconnect comprising:   a multiport register; and   a cross-point switch for configuration of a data path.   
   
   
       61 . The apparatus of  claim 48 , further comprising:
 a post-processing circuit to match a plurality of line or curve segments of a boundary of the graphical image and to determine a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image.   
   
   
       62 . The apparatus of  claim 48 , further comprising:
 a graphics rendering circuit to apply a fill style to generate pixel data for an area of the graphical image.   
   
   
       63 . The apparatus of  claim 62 , wherein the execution circuit is further configured to apply a line style by forming a second graphical image from a boundary of the graphical image, and wherein the graphics rendering circuit is further configured to apply a fill style to the second graphical image to generate pixel data for the line style. 
   
   
       64 . The apparatus of  claim 48 , further comprising:
 a first processor to separate the action script from other data.   
   
   
       65 . The apparatus of  claim 64 , wherein the first processor is further configured to perform hypertext transfer protocol (“HTTP”) for reception of a data file and to generate pixel data for hypertext markup language (“HTML”) or extensible markup language (“XML”) data of the data file. 
   
   
       66 . The apparatus of  claim 65 , further comprising:
 a frame buffer;   wherein the graphics rendering circuit is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the first processor is further configured to transfer the pixel data for the HTML or XML data to the frame buffer.   
   
   
       67 . The apparatus of  claim 65 , further comprising:
 a frame buffer; and   a visual display;   wherein the graphics rendering circuit is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the first processor is further configured to transfer the pixel data for the HTML or XML data to the visual display.   
   
   
       68 . The apparatus of  claim 65 , further comprising:
 a frame buffer; and   a display controller;   wherein the graphics rendering circuit is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the first processor is further configured to transfer the pixel data for the HTML or XML data to the display controller.   
   
   
       69 . The apparatus of  claim 48 , wherein the plurality of descriptive elements are a specification of at least one graphical image in a form which at least partially is not pixel-by-pixel; wherein each operational code of the plurality of operational codes is a hardware-level instruction or hardware-decodable into a plurality of hardware-level microcode, or hardware-level binary instructions, or hardware-level control signals; wherein the action script is a data file which has not been fully compiled to machine code and which comprises at least one descriptive element; and wherein the graphical image is an image of any kind for visual display which has been specified at least partially in a non-pixel-by-pixel form in the action script. 
   
   
       70 . A system for processing an action script for visual display of a graphical image, the system comprising:
 a network input and output interface configured to receive data;   a first memory circuit;   first circuitry configured to convert a plurality of descriptive elements of the action script into a plurality of operational codes;   second circuitry configured to perform an operation corresponding to an operational code of the plurality of operational codes using corresponding data stored in the first memory to generate pixel data for the graphical image; and   a frame buffer to store the pixel data.   
   
   
       71 . The system of  claim 70 , further comprising:
 a display controller coupled to the frame buffer to receive the pixel data; and   a display coupled to the display controller and configured to visually display the graphical image.   
   
   
       72 . The system of  claim 70 , further comprising:
 third circuitry configured to parse the action script into the plurality of descriptive elements and the corresponding data.   
   
   
       73 . The system of  claim 72 , further comprising:
 fourth circuitry configured to decode a descriptive element to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script.   
   
   
       74 . The system of  claim 72 , wherein the third circuitry further comprises:
 a decoder configured to determine a type of descriptive element;   a parsing controller coupled to the decoder and configured to determine or select a number of bits to parse parameter;   a stream register configured to store a plurality of bits of the action script; and   at least one barrel shifter configured to shift out of the stream register a number of bits designated by the number of bits to parse parameter.   
   
   
       75 . The system of  claim 70 , further comprising:
 fifth circuitry configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.   
   
   
       76 . The system of  claim 75 , wherein each control word of the plurality of control words comprises:
 a starting or an ending x-coordinate and y-coordinate for a corresponding line or curve segment for the graphical image;   a first memory address for line style array for a corresponding line or curve segment for the graphical image; and   a second memory address for fill style array for a plurality of line or curve segments comprising the graphical image.   
   
   
       77 . The system of  claim 70 , further comprising:
 sixth circuitry configured to decode each operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control the second circuitry to perform a selected operation, of a plurality of operations, corresponding to a selected operational code of the plurality of operational codes.   
   
   
       78 . The system of  claim 70 , wherein the second circuitry further comprises
 at least one arithmetic logic unit; and   at least one floating point circuit.   
   
   
       79 . The system of  claim 70 , further comprising:
 a configurable interconnect coupled to the at least one arithmetic logic unit and to the at least one floating point execution unit, the configurable interconnect comprising:   a multiport register; and   a cross-point switch for configuration of a data path.   
   
   
       80 . The system of  claim 70 , further comprising:
 seventh circuitry configured to match a plurality of line or curve segments of a boundary of the graphical image and to determine a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image.   
   
   
       81 . The system of  claim 70 , further comprising:
 eighth circuitry configured to separate the action script from other received data;   ninth circuitry configured to perform hypertext transfer protocol (“HTTP”); and   tenth circuitry configured to generate pixel data for hypertext markup language (“HTML”) or extensible markup language (“XML”) data of the data file.   
   
   
       82 . The system of  claim 81 , wherein the second circuitry is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the tenth circuitry is further configured to transfer the pixel data for the HTML or XML data to the frame buffer. 
   
   
       83 . The system of  claim 81 , further comprising:
 a visual display;   wherein the second circuitry is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the tenth circuitry is further configured to transfer the pixel data for the HTML or XML data to the visual display.   
   
   
       84 . The system of  claim 81 , further comprising:
 a display controller;   wherein the second circuitry is further configured to transfer the pixel data for the graphical image to the frame buffer and wherein the tenth circuitry is further configured to transfer the pixel data for the HTML or XML data to the display controller.   
   
   
       85 . The system of  claim 81 , wherein the first circuitry, the second circuitry, the eighth circuitry, the ninth circuitry, and the tenth circuitry are embodied in a single integrated circuit. 
   
   
       86 . The system of  claim 81 , wherein the first circuitry, the second circuitry, the eighth circuitry, the ninth circuitry, and the tenth circuitry further comprise a plurality of processor cores. 
   
   
       87 . A hardware-implemented method of processing an action script for visual display of a graphical image, the method comprising:
 parsing the action script into a plurality of descriptive elements and a corresponding data;   storing the corresponding data in a hardware memory;   converting the plurality of descriptive elements to a plurality of operational codes which control execution circuitry; and   using the execution circuitry, performing an operation corresponding to an operational code of the plurality of operational codes using the corresponding data to generate pixel data for the graphical image.   
   
   
       88 . The hardware-implemented method of  claim 87 , further comprising:
 separating the action script from other data.   
   
   
       89 . The hardware-implemented method of  claim 87 , further comprising:
 decoding a descriptive element of the action script to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script.   
   
   
       90 . The hardware-implemented method of  claim 89 , wherein the converting step further comprises:
 performing a hash operation on each descriptive element of the plurality of descriptive elements to generate a corresponding hash result; and   using the hash result to determine a corresponding operational code of the plurality of operational codes.   
   
   
       91 . The hardware-implemented method of  claim 89 , wherein the parsing step further comprises:
 determining a type of descriptive element;   determining or selecting a number of bits to parse to form a number of bits to parse parameter; and   shifting out of the stream register a number of bits designated by the number of bits to parse parameter.   
   
   
       92 . The hardware-implemented method of  claim 87 , wherein the parsing step further comprises:
 extracting data from the action script and storing the extracted data in the hardware memory in the form of a plurality of control words having the corresponding data in predetermined fields.   
   
   
       93 . The hardware-implemented method of  claim 87 , wherein the plurality of descriptive elements are a plurality of tags or bytecodes. 
   
   
       94 . The hardware-implemented method of  claim 87 , wherein the performing step further comprises:
 decoding a selected operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control the execution circuit to perform a selected operation, of a plurality of operations, corresponding to the selected operational code of the plurality of operational codes.   
   
   
       95 . The hardware-implemented method of  claim 87 , further comprising:
 matching a plurality of line or curve segments of a boundary of the graphical image; and   determining a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image.   
   
   
       96 . The hardware-implemented method of  claim 87 , further comprising:
 applying a fill style to generate pixel data for an area of the graphical image.   
   
   
       97 . The hardware-implemented method of  claim 87 , further comprising:
 applying a line style by forming a second graphical image from a boundary of the graphical image; and   applying a fill style to the second graphical image to generate pixel data for the line style.   
   
   
       98 . The hardware-implemented method of  claim 87 , further comprising:
 generating pixel data for hypertext markup language (“HTML”) or extensible markup language (“XML”) data.   
   
   
       99 . The hardware-implemented method of  claim 98 , further comprising:
 merging the pixel data for the graphical image with pixel data for the hypertext markup language (“HTML”) or extensible markup language (“XML”) data.   
   
   
       100 . A system for processing an action script for visual display of a graphical image, the system comprising:
 a network input and output interface configured to receive a data file;   a user input and output interface;   a first memory;   a frame buffer to store the pixel data;   first circuitry to separate the action script from other data;   second circuitry to parse the action script into the plurality of descriptive elements and corresponding data and to store the corresponding data in the first memory as a plurality of control words having the corresponding data in predetermined fields;   third circuitry to convert a plurality of descriptive elements of the action script into a plurality of hardware operational codes;   fourth circuitry to perform an operation corresponding to an operational code of the plurality of hardware operational codes using the corresponding data stored in the first memory to generate first pixel data for the graphical image and to transfer the first pixel data to the frame buffer; and   fifth circuitry configured to generate second pixel data for hypertext markup language (“HTML”) or extensible markup language (“XML”) data of the data file and to transfer the second pixel data to the frame buffer.