Vertical channel type nonvolatile memory device and method for fabricating the same

Abstract

A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.

1 . A method for fabricating a vertical channel type nonvolatile memory device, the method comprising:
 alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate;   etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel, each of which exposes the semiconductor substrate;   filling the first openings to form a plurality of channels protruding from the semiconductor substrate;   etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels;   exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and   forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.   
     
     
         2 . The method of  claim 1 , wherein the sacrificial layers comprise a material having a high etch selectivity ratio to the interlayer dielectric layers. 
     
     
         3 . The method of  claim 2 , wherein the sacrificial layers comprise a nitride layer or an amorphous carbon layer, and the interlayer dielectric layers comprise an oxide layer. 
     
     
         4 . The method of  claim 1 , wherein the second openings for removal of the sacrificial layers comprise a plurality of line type openings expending in parallel in a certain direction, or a plurality of hole type openings arranged in a first direction and a second direction intersecting with the first direction. 
     
     
         5 . The method of  claim 1 , wherein the second openings for removal of the sacrificial layers are formed to a depth at which at least the most lowest sacrificial layer is exposed. 
     
     
         6 . The method of  claim 1 , wherein the channels comprise a single crystal silicon layer or a polycrystal silicon layer. 
     
     
         7 . The method of  claim 1 , wherein the tunnel insulation layer, the charge trap layer, and the charge blocking layer are formed as spacers between the conductive layer for gate electrode and the interlayer dielectric layer. 
     
     
         8 . The method of  claim 7 , wherein the spacers comprises an oxide-nitride-oxide (ONO) layer. 
     
     
         9 . The method of  claim 1 , wherein forming the tunnel insulation layer, the charge trap layer, the charge blocking layer, and the conductive layer for gate electrode comprises:
 forming the tunnel insulation layer, the charge trap layer, and the charge blocking layer on a space having a opened region between the interlayer dielectric layers where the sacrificial layers are removed;   forming the conductive layer for gate electrode over a resulting structure to fill the opened region between the interlayer dielectric layers;   forming a plurality of mask patterns over a resulting structure including the conductive layer for gate electrode, wherein the mask patterns covering a region where memory cells are to be formed and extending in a certain direction; and   forming a plurality of gate electrodes by etching the conductive layer for gate electrode using the mask patterns as an etch barrier.   
     
     
         10 . The method of  claim 1 , further comprises:
 forming the tunnel insulation layer, the charge trap layer, and the charge blocking layer over a resulting structure where the sidewalls of the channels are exposed, a region between the interlayer dielectric layers being opened;   filling the opened region between the interlayer dielectric layers with the conductive layer for gate electrode to form a plurality of gate electrodes of memory cells; and   filling the second openings for removal of the sacrificial layers with a insulation layer where the gate electrodes are formed.   
     
     
         11 . The method of  claim 10 , wherein the forming the plurality of gate electrodes comprises:
 forming the conductive layer for gate electrode to open a center region of the second openings for removal of the sacrificial layers; and   separating the gate electrodes by removing the conductive layers for gate electrode which are formed along inner sidewalls of the opened center region.   
     
     
         12 . The method of  claim 1 , wherein the forming the tunnel insulation layer, the charge trap layer, the charge blocking layer, and the conductive layer for gate electrode comprises:
 forming the tunnel insulation layer, the charge trap layer, and the charge blocking layer over a resulting structure where the sidewalls of the channels are exposed, a region between the interlayer dielectric layers being opened;   forming the conductive layer for gate electrode over a resulting structure to fill the opened region between the interlayer dielectric layers;   selectively etching the conductive layer for gate electrode to separate a plurality of gate electrodes of memory cells; and   forming an insulation layer to fill a region where the conductive layer for gate electrode is etched.   
     
     
         13 . The method of  claim 1 , further comprising:
 forming a plurality of bit lines connected to the channels, after forming the tunnel insulation layer, the charge trap layer, the charge blocking layer, and the conductive layer for gate electrode.   
     
     
         14 . The method of  claim 1 , wherein forming the tunnel insulation layer, the charge trap layer, the charge blocking layer, and the conductive layer for gate electrode comprises:
 patterning the previously formed layers to expose a plurality of gate electrodes of memory cells; and   forming a plurality of word lines connected to the gate electrodes of the memory cells.   
     
     
         15 . A method for fabricating a vertical channel type nonvolatile memory device, the method comprising:
 alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate;   etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel, each of which exposes the semiconductor substrate;   filling the first openings to form a plurality of rectangular pillar type channels protruding from the substrate;   etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers which are disposed between the channels;   exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and   forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.   
     
     
         16 . The method of  claim 15 , wherein the forming the plurality of first openings for channel comprises:
 etching the sacrificial layers and the interlayer dielectric layers to form a plurality of line type openings extending in parallel in a first direction;   filling the line type openings with an insulation layer;   forming a plurality of mask patterns extending in parallel in a second direction intersecting with the first direction over a resulting structure where the insulation layer is formed; and   forming the plurality of rectangular pillar type first openings by etching the insulation layer using the mask patterns as an etch barrier.   
     
     
         17 . The method of  claim 15 , wherein the forming a plurality of rectangular pillar type channels comprises:
 filling the line type first openings to form the channels;   forming a plurality of mask patterns extending in parallel in a second direction intersecting with the first direction over a resulting structure where the layer for channel is formed;   forming the plurality of rectangular pillar type channels by etching the channels using the mask patterns as an etch barrier; and   forming an insulation layer to fill a region where the layer for channel is etched.   
     
     
         18 . The method of  claim 15 , wherein the second openings for removal of the sacrificial layer comprise a plurality of line type openings extending in parallel in a certain direction, or a plurality of hole type openings arranged in a first direction and a second direction intersecting with the first direction. 
     
     
         19 . The method of  claim 15 , wherein the tunnel insulation layer, the charge trap layer, and the charge blocking layer are formed, as a spacer, between the conductive layer for gate electrode and the interlayer dielectric layer. 
     
     
         20 . The method of  claim 19 , wherein the spacer comprises an oxide-nitride-oxide (ONO) layer. 
     
     
         21 . The method of  claim 15 , wherein the forming the tunnel insulation layer, the charge trap layer, the charge blocking layer, and the conductive layer for gate electrode comprises:
 forming the tunnel insulation layer, the charge trap layer, and the charge blocking layer over a resulting structure where the sacrificial layers are removed, a region between the interlayer dielectric layers being opened;   forming the conductive layer for gate electrode over a resulting structure to fill the opened region between the interlayer dielectric layers;   forming a plurality of mask patterns over a resulting structure where the conductive layer for gate electrode is formed, the mask patterns covering a region where memory cells are to be formed and extending in a certain direction; and   forming a plurality of gate electrodes by etching the conductive layer for gate electrode using the mask patterns as an etch barrier.   
     
     
         22 . The method of  claim 15 , wherein the forming the tunnel insulation layer, the charge trap layer, the charge blocking layer, and the conductive layer for gate electrode comprises:
 sequentially forming the tunnel insulation layer, the charge trap layer, and the charge blocking layer over a resulting structure where the sidewalls of the channels are exposed, a region between the interlayer dielectric layers being opened;   filling the opened region between the interlayer dielectric layers with the conductive layer for gate electrode to form a plurality of gate electrodes of memory cells stacked along the channels; and   forming an insulation layer to fill the second openings where the gate electrodes are formed.   
     
     
         23 . The method of  claim 22 , wherein the forming the plurality of gate electrodes comprises:
 forming the conductive layer for gate electrode to open a center region of the second openings; and   separating the gate electrodes by removing the conductive layers for gate electrode which are formed along inner sidewalls of the opened center region.   
     
     
         24 . The method of  claim 15 , wherein the forming the tunnel insulation layer, the charge trap layer, the charge blocking layer, and the conductive layer for gate electrode comprises:
 forming the tunnel insulation layer, the charge trap layer, and the charge blocking layer over a resulting structure where the sidewalls of the channels are exposed, a region between the interlayer dielectric layers being opened;   forming the conductive layer for gate electrode over a resulting structure to fill the opened region between the interlayer dielectric layers;   selectively etching the conductive layer for gate electrode to separate a plurality of gate electrodes of memory cells stacked along the channels; and   forming an insulation layer to fill a region where the conductive layer for gate electrode is etched.   
     
     
         25 . A vertical channel type nonvolatile memory device, comprising:
 a plurality of channels protruding from a semiconductor substrate; and   a plurality of strings comprising a plurality of memory cells stacked along the channels,   wherein at least two of the strings share one channel.   
     
     
         26 . The vertical channel type nonvolatile memory device of  claim 25 , wherein the channels are arranged in a first direction and a second direction intersecting with the first direction, and an insulation layer is buried in a region between the channels arranged in the first direction. 
     
     
         27 . The vertical channel type nonvolatile memory device of  claim 25 , wherein the channels have a rectangular pillar type, and the two strings sharing one channel are formed on both sides of the rectangular pillar type channels. 
     
     
         28 . A vertical channel type nonvolatile memory device, comprising:
 a channel protruding from a semiconductor substrate;   a string comprising a plurality of memory cells stacked along the channel; and   a spacer on sidewalls of gate electrodes of the memory cells.   
     
     
         29 . The vertical channel type nonvolatile memory device of  claim 28 , wherein the spacer comprises an oxide-nitride-oxide (ONO) layer. 
     
     
         30 . A vertical channel type nonvolatile memory device, comprising:
 a channel protruding from a semiconductor substrate; and   a string comprising a plurality of memory cells stacked along the channel,   wherein the memory cells disposed on the same layer operate as one page.   
     
     
         31 . The vertical channel type nonvolatile memory device of  claim 30 , wherein the memory cells disposed on the same layer share a gate electrode. 
     
     
         32 . The vertical channel type nonvolatile memory device of  claim 30 , wherein the memory cell comprises:
 a gate electrode alternately stacked with interlayer dielectric layer over a semiconductor substrate;   a channel buried within a plurality of gate electrode and interlayer dielectric layer and protruding from the semiconductor substrate; and   a tunnel insulation layer, a charge trap layer, and a charge blocking layer disposed between sidewalls of the channels of the gate electrodes, and   the gate electrodes in the memory cells stacked along the channels are separated by a gate electrode separation layer buried within the gate electrode and the interlayer dielectric layer.