Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

1 . A semiconductor integrated circuit device comprising a semiconductor chip,
 the semiconductor chip comprising:   a plurality of I/O pads disposed along edges of the semiconductor chip; and   a plurality of I/O parts disposed over the semiconductor chip and coupled with any of the I/O pads,   the I/O parts each comprising:   an output buffer block including an N-channel transistor and a P-channel transistor to form an output buffer and functioning as an interface for output of signals to the outside; and   a logic block for controlling the output buffer block and an input buffer block,   wherein in the I/O part, the logic block, the N-channel transistor, and the P-channel transistor are arranged toward an edge of the semiconductor chip in order, and   wherein a pad lead part to be coupled with the I/O pad lies between the logic block and the N-channel transistor.   
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein in the N-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the N-channel transistor to have a high resistance. 
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 ,
 wherein the output buffer block includes a first and a second diode for ESD protection, and   wherein the first and second diodes lie between the N-channel transistor and the P-channel transistor.   
     
     
         4 . The semiconductor integrated circuit device according to  claim 3 ,
 wherein the output buffer block has a resistance for ESD protection, and   wherein the resistance lies between the first and second diodes and the P-channel transistor.   
     
     
         5 . The semiconductor integrated circuit device according to  claim 1 , wherein in the P-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the P-channel transistor to have a high resistance. 
     
     
         6 . A semiconductor integrated circuit device comprising a semiconductor chip,
 the semiconductor chip comprising:   a plurality of I/O pads disposed along edges of the semiconductor chip; and   a plurality of I/O parts disposed over the semiconductor chip and coupled with any of the I/O pads,   the I/O parts each comprising:   an output buffer block including an N-channel transistor and a P-channel transistor to form an output buffer and functioning as an interface for output of signals to the outside; and   a logic block which includes an input buffer block functioning as an interface for input of signals from the outside, and controls the output buffer block and the input buffer block,   wherein in the I/O part, the logic block, the P-channel transistor, and the N-channel transistor are arranged in line in order, and   wherein a pad lead part to be coupled with the I/O pad lies between the logic block and the P-channel transistor.   
     
     
         7 . The semiconductor integrated circuit device according to  claim 6 , wherein in the N-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the N-channel transistor to have a high resistance. 
     
     
         8 . The semiconductor integrated circuit device according to  claim 6 ,
 wherein the output buffer block includes a first and a second diode for ESD protection, and   wherein the first and second diodes lie between the N-channel transistor and the P-channel transistor.   
     
     
         9 . The semiconductor integrated circuit device according to  claim 8 ,
 wherein the output buffer block has a resistance for ESD protection, and   wherein the resistance lies between the first and second diodes and the P-channel transistor.   
     
     
         10 . The semiconductor integrated circuit device according to  claim 6 , wherein in the P-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the P-channel transistor to have a high resistance. 
     
     
         11 . The semiconductor integrated circuit device according to  claim 2 ,
 wherein the output buffer block includes a first and a second diode for ESD protection, and   wherein the first and second diodes lie between the N-channel transistor and the P-channel transistor.   
     
     
         12 . The semiconductor integrated circuit device according to  claim 11 ,
 wherein the output buffer block has a resistance for ESD protection, and   wherein the resistance lies between the first and second diodes and the P-channel transistor.   
     
     
         13 . The semiconductor integrated circuit device according to  claim 2 , wherein in the P-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the P-channel transistor to have a high resistance. 
     
     
         14 . The semiconductor integrated circuit device according to  claim 3 , wherein in the P-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the P-channel transistor to have a high resistance. 
     
     
         15 . The semiconductor integrated circuit device according to  claim 11 , wherein in the P-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the P-channel transistor to have a high resistance. 
     
     
         16 . The semiconductor integrated circuit device according to  claim 7 ,
 wherein the output buffer block includes a first and a second diode for ESD protection, and   wherein the first and second diodes lie between the N-channel transistor and the P-channel transistor.   
     
     
         17 . The semiconductor integrated circuit device according to  claim 16 ,
 wherein the output buffer block has a resistance for ESD protection, and   wherein the resistance lies between the first and second diodes and the P-channel transistor.   
     
     
         18 . The semiconductor integrated circuit device according to  claim 7 , wherein in the P-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the P-channel transistor to have a high resistance. 
     
     
         19 . The semiconductor integrated circuit device according to  claim 8 , wherein in the P-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the P-channel transistor to have a high resistance. 
     
     
         20 . The semiconductor integrated circuit device according to  claim 16 , wherein in the P-channel transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, in order for a drain terminal of the P-channel transistor to have a high resistance.