Efficient and Secure Main Memory Sharing Across Multiple Processors

Abstract

Various embodiments of the present invention provide systems and methods for using providing memory access across multiple virtual machines. For example, various embodiments of the present invention provide computing systems that include at least two processors each communicably coupled to a network switch via network interfaces. The computing systems further include a memory appliance communicably coupled to the network switch, and configured to operate as a main memory for the two or more processors.

1 . A computing system, the computing system comprising:
 a first processor communicably coupled to a network switch via a first network interface;   a second processor communicably coupled to the network switch via a second network interface; and   a memory appliance communicably coupled to the network switch, wherein the memory appliance is configured to operate as a main memory for both the first processor and the second processor.   
   
   
       2 . The computing system of  claim 1 , wherein the first processor is coupled to a first cache, and wherein the second processor is coupled to a second cache. 
   
   
       3 . The computing system of  claim 1 , wherein the system further comprises:
 a first random access memory electrically coupled to the first processor; and   a second random access memory electrically coupled to the second processor.   
   
   
       4 . The computing system of  claim 3 , wherein:
 the first random access memory is a mounted on a first DIMM package; and   the second random access memory is mounted on a second DIMM package.   
   
   
       5 . The computing system of  claim 1 , wherein the system further comprises:
 a hard disk drive, wherein the hard disk drive is communicably coupled to the network switch, and wherein the hard disk drive is accessible to both the first processor and the second processor.   
   
   
       6 . The computing system of  claim 1 , wherein the system further comprises:
 a hard disk drive electrically coupled to the memory appliance, and wherein the hard disk drive is accessible to both the first processor and the second processor.   
   
   
       7 . The computing system of  claim 1 , wherein the memory appliance includes a network interface and a flash memory. 
   
   
       8 . The computing system of  claim 7 , wherein the memory appliance further includes a DRAM. 
   
   
       9 . The computing system of  claim 1 , wherein the memory appliance includes a network interface and a DRAM. 
   
   
       10 . The computing system of  claim 1 , wherein the memory appliance is a first memory appliance, and wherein the system further comprises:
 a second memory appliance communicably coupled to the network switch, wherein the second memory appliance is configured to operate as a main memory for both the first processor and the second processor.   
   
   
       11 . A method for providing main memory in a computing system, the method comprising:
 providing a memory appliance, wherein the memory appliance includes a randomly accessible memory space;   communicably coupling a first processor to the memory appliance via a network interface;   communicably coupling a second processor to the memory appliance via the network interface;   allocating a first portion of the randomly accessible memory space to the first processor; and   allocating a second portion of the randomly accessible memory space to the second processor.   
   
   
       12 . The method of  claim 11 , wherein the randomly accessible memory space is a first randomly accessible memory space, wherein the first processor is electrically coupled to a second randomly accessible memory space. 
   
   
       13 . The method of  claim 12 , wherein a main memory associated with the first processor includes a combination of the first portion of the first randomly accessible memory space and the second randomly accessible memory space. 
   
   
       14 . The method of  claim 13 , wherein the real address space supported by the first portion of the first randomly accessible memory space is exclusive of the real address space supported by the second randomly accessible memory space. 
   
   
       15 . The method of  claim 11 , wherein the first portion of the randomly accessible memory space does not overlap the second portion of the randomly accessible memory space. 
   
   
       16 . The method of  claim 11 , wherein the first portion of the randomly accessible memory space at least partially overlaps the second portion of the randomly accessible memory space. 
   
   
       17 . The method of  claim 11 , wherein the first processor is electrically coupled to a first cache, and wherein the second processor is electrically coupled to a second cache. 
   
   
       18 . The method of  claim 11 , wherein the memory appliance is a first memory appliance, wherein the randomly accessible memory space is a first randomly accessible memory space, and wherein the method further comprises:
 providing a second memory appliance, wherein the second memory appliance includes a second randomly accessible memory space;   communicably coupling the first processor to the second memory appliance via the network interface; and   allocating a portion of the second randomly accessible memory space to the first processor.   
   
   
       19 . A network based main memory system, the memory system comprising:
 a network switch;   a memory appliance including a randomly accessible memory space and a network interface, wherein the memory appliance is communicably coupled to the network switch;   a first processor communicably coupled to the memory appliance via the network switch, wherein the first processor is allocated a first portion of the randomly accessible memory space; and   a second processor communicably coupled to the memory appliance via the network switch, wherein the second processor is allocated a second portion of the randomly accessible memory space.   
   
   
       20 . The network based main memory system, wherein the randomly accessible memory space is a first randomly accessible memory space, wherein the memory system further includes:
 a second randomly accessible memory space directly coupled to the first processor, wherein the real address space supported by the first portion of the first randomly accessible memory space is exclusive of the real address space supported by the second randomly accessible memory space.