Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features

Abstract

The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

1 - 20 . (canceled) 
   
   
       21 . A portion of a digital integrated circuit, comprising:
 a memory block comprised of a plurality of memory bit-cells; and,   a plurality of logic bricks that perform logic functions;   wherein said bricks share common geometric patterns, and have sizes and patterns that have been optimized for compatibility with illumination control settings used for the lithography of the memory bit-cells.   
   
   
       22 . A portion of a digital integrated circuit as defined in  claim 21 , wherein the logic bricks are formed by mapping a restricted set of logic primitives onto areas of a regular geometric fabric. 
   
   
       23 . A portion of a digital integrated circuit as defined in  claim 21 , wherein boundaries are controlled so that common geometrical patterns appear among neighboring logic bricks that are printed. 
   
   
       24 . A portion of a digital integrated circuit as defined in  claim 21 , wherein the physical design of a brick can be evaluated for printability in silicon independently of the other bricks that will ultimately be printed in its neighborhood. 
   
   
       25 . A portion of a digital integrated circuit as defined in  claim 21 , wherein said bricks are derived from an underlying fabric of regular geometry patterns from which all geometrical shapes for all devices and interconnections are also derived. 
   
   
       26 . A portion of a digital integrated circuit as defined in  claim 25 , wherein said bricks are derived from said underlying fabric by a process that is equivalent to removing selected patterns and adding vias in restricted locations to connect neighboring layers. 
   
   
       27 . A method for designing integrated circuits using regular geometry patterns, the method comprising:
 providing a fabric of regular patterns derived for a particular technology with technology-specific settings, the patterns optimized for compatibility with illumination control settings that will be used for the lithography of memory blocks;   using the fabric to create logic brick representations; and,   using the fabric to render a compiled a memory block.   
   
   
       28 . The method of  claim 27 , wherein each of the logic brick representations represents a small logic function comprised of patterns derived from the fabric. 
   
   
       29 . The method of  claim 27 , wherein using the fabric to create logic brick representations comprises deriving the logic brick representations from a combination of fabric constraints and logic requirements derived from logic synthesis. 
   
   
       30 . The method of  claim 27 , further comprising:
 performing floorplanning and physical mapping to map the memory block and logic brick representations onto the fabric for output in GDSII form.   
   
   
       31 . The method of  claim 27 , wherein the technology-specific settings include effective channel length. 
   
   
       32 . The method of  claim 27 , wherein the technology-specific settings include a leakage target. 
   
   
       33 . The method of  claim 27 , further comprising:
 before providing the fabric of regular patterns, first fabricating silicon test structures that include the patterns of geometrical shapes from which the fabric is defined.   
   
   
       34 . The method of  claim 27 , further comprising:
 changing the technology-specific setting(s); and,   providing a new fabric based on the changed technology-specific setting(s).   
   
   
       35 . The method of  claim 34 , wherein the changed technology-specific setting(s) include a lower leakage target. 
   
   
       36 . The method of  claim 34 , further comprising:
 recompiling the logic brick representations and memory block(s) onto the new fabric, without requiring a complete redesign of the integrated circuit.   
   
   
       37 . A computer-readable medium containing a GDSII representation of an integrated circuit, said GDSII representation including:
 a plurality of logic brick representations; and,   at least one compiled memory block that includes memory cells;   wherein said plurality of logic brick representations and said compiled memory block consist essentially of geometrical shapes derived from an underlying fabric of regular geometry patterns that have been optimized for compatibility with illumination control settings that will be used for the lithography of the memory cells in the compiled memory block.   
   
   
       38 . The computer-readable medium of  claim 37 , wherein said GDSII representation further includes interconnections that also consist essentially of geometrical shapes derived from the underlying fabric of regular geometry patterns. 
   
   
       39 . The computer-readable medium of  claim 37 , wherein the boundaries among neighboring logic brick representations in the GDSII representation consist essentially of common geometrical patterns. 
   
   
       40 . The computer-readable medium of  claim 37 , wherein the GDSII representation represents a manufacturable-by-construction design.