Array substrate for display device and method of manufacturing the same

Abstract

An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line and a source electrode and a drain electrode formed on the semiconductor layer. The capacitor electrode is overlapped with the data line. The source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode include a transparent conductive material.

1 . A method of manufacturing an array substrate, the method comprising:
 forming a data line on a substrate;   forming a passivation layer on the data line;   forming a gate line including a gate electrode and a capacitor line on the passivation layer, wherein the capacitor electrode is overlapped with the data line;   forming a gate insulation layer on the gate line and the capacitor line;   forming a semiconductor layer on the gate insulation layer;   forming a contact hole through the passivation layer and the gate insulation layer to expose the data line; and   forming a source electrode and a drain electrode on the semiconductor layer,   wherein the source electrode is connected to the data line through the contact hole, and the source electrode and the drain electrode comprises a transparent conductive material.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming an ohmic contact layer between the semiconductor layer and the source electrode and the drain electrode.   
     
     
         3 . The method of  claim 1 , wherein the transparent conductive material comprises one of a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO). 
     
     
         4 . The method of  claim 1 , wherein a width of the capacitor line is wider than a width of the data line. 
     
     
         5 . The method of  claim 1 , wherein the semiconductor layer is formed on an island shape on the gate insulation layer. 
     
     
         6 . The method of  claim 1 , wherein the semiconductor layer comprises at least one of amorphous silicon and polycrystalline silicon. 
     
     
         7 . The method of  claim 1 , wherein the semiconductor layer comprises a mixed oxide at least one of ZnO, InZO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, and GaInZnO. 
     
     
         8 . A method of manufacturing a display device, the method comprising:
 forming a first substrate, wherein forming the first substrate comprises:   forming a data line on the substrate;   forming a passivation layer on the data line;   forming a gate line including a gate electrode and a capacitor line that is formed on the passivation layer and is overlapped with the data line;   forming a gate insulation layer on the gate line and the capacitor line;   forming a semiconductor layer on the gate insulation layer;   forming a contact hole through the passivation layer and the gate insulation layer to expose the data line; and   forming a source electrode and a drain electrode on the semiconductor layer,   forming a second substrate including a black matrix; and   forming a liquid crystal layer between the first substrate and the second substrate, wherein the drain electrode comprises a pixel electrode formed on the gate insulation layer, and a distance of adjacent pixel electrodes is narrower than a width of the black matrix, a width of the capacitor line and a width of the data line.   
     
     
         9 . The method of  claim 8 , further comprising:
 forming an ohmic contact layer between the semiconductor layer and the source electrode and the drain electrode.   
     
     
         10 . The method of  claim 8 , wherein the pixel electrode comprises one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO). 
     
     
         11 . The method of  claim 8 , wherein a width of the capacitor line is wider than a width of the data line. 
     
     
         12 . The method of  claim 11 , wherein the capacitor line entirely covers the data line. 
     
     
         13 . The method of  claim 8 , wherein the semiconductor layer is formed on an island shape on the gate insulation layer. 
     
     
         14 . The method of  claim 8 , wherein the semiconductor layer comprises at least one of amorphous silicon and polycrystalline silicon. 
     
     
         15 . The method of  claim 8 , wherein the semiconductor layer comprises a mixed oxide at least one of ZnO, InZO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, and GaInZnO.