Removable Mother/Daughter Peripheral Card

Abstract

A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

1 . A non-volatile memory device assembly, comprising:
 a memory card comprising:   a first connector;   a flash array;   compressed user data stored in a first portion of the array; and   information useful to decompress the compressed user data stored in a second portion of the array; and   a mother card comprising:   a second connector, whereby the mother card is removably connectable to the memory card by connecting of the first and second connectors to one another;   a third connector whereby the mother card can be removably coupled to a host, wherein the third memory connector uses a different pin connector structure from the first connectors pin connector structure; and   a module having a controller function that decompresses the compressed user data using said information when the mother card is removably coupled to the host and the memory card is removably connectable to the mother card, the user data being transferrable from the memory card to the host via the mother card,   wherein the information useful to decompress the stored compressed user data includes a decompression algorithm used by the module to decompress the compressed user data,   wherein the host and the memory card lack the memory controller function, and   wherein the memory card receives from the mother card through the second and first connectors program and erase voltages for respective use in storing data in, and erasing of data from, the array.   
   
   
       2 . The assembly of  claim 1 , wherein the mother card further includes power conversion circuitry for generating the program and erase voltages. 
   
   
       3 . The assembly of  claim 1 , where the mother card further includes a flash system controller circuit. 
   
   
       4 . The assembly of  claim 1 , wherein the memory card serves as the main memory for the host. 
   
   
       5 . The assembly of  claim 1 , wherein the memory card includes a communication device. 
   
   
       6 . A method of storing user data on and retrieving user data from a non-volatile memory card, comprising:
 compressing the user data;   storing both the compressed user data and information useful to decompress the compressed user data on the memory card, the information being also useful for compressing the user data;   thereafter reading both the compressed user data and the information from the memory card; and   decompressing the read compressed user data by use of the read information, to thereby to obtain the user data,   wherein the information stored on the memory card includes a decompression algorithm, and   wherein at least one of the compressing and decompressing are performed using the information in a memory controller function present in a mother card to which the memory card is removably connectable while the mother card is removably coupled to a first host, the user data is being transferred between the memory card and the first host via the mother card, and   wherein the first host and the memory card lack the memory controller function.   
   
   
       7 . The method of  claim 6 , wherein the non-volatile memory card includes a flash EEPROM array, and both the compressed user data and the information are stored in the flash EEPROM array. 
   
   
       8 . The method of  claim 7 , wherein the storing includes programming both the compressed user data and information into individual memory cells of the flash EEPROM array in more than two states, thereby to store more than one bit of said user data and information per cell. 
   
   
       9 . The method of  claim 6 , wherein the compressing and storing occur when the mother card is electrically connected to the first host, and wherein the reading and decompressing occur when the memory card is electrically connected to a second host. 
   
   
       10 . The method of  claim 9 , wherein the compressing is performed by the mother card and the decompressing is performed by the second host system. 
   
   
       11 . The method of  claim 6 , further comprising connecting the mother card with a plurality of personal computer cards, so that the mother card is simultaneously connected with a plurality of personal computer cards. 
   
   
       12 . The method of  claim 6 , wherein at least one of the compressing and decompressing are performed in a hardware circuit in the mother card. 
   
   
       13 . The method of  claim 6 , wherein the compressing and storing occur when the memory card is electrically connected to a second host, and wherein the reading and decompressing occur when the mother card is electrically connected to the first host. 
   
   
       14 . The method of  claim 13 , wherein either the compressing is performed by the second host and the decompressing is performed by the mother card. 
   
   
       15 . A non-volatile memory device assembly, comprising:
 a memory card comprising:
 a flash array; 
 compressed user data stored in a first portion of the array; and 
 information useful to decompress the compressed user data stored in a second portion of the array; and 
   a mother card comprising a module having a controller function that decompresses the compressed user data using said information when the mother card is removably coupled to a host and the memory card is removably connectable to the mother card, the user data being transferrable from the memory card to the host via the mother card,   wherein the information useful to decompress the stored compressed user data includes a decompression algorithm used by the module to decompress the compressed user data, and   wherein the host and the memory card lack the memory controller function.   
   
   
       16 . The assembly of  claim 15 , wherein the flash array comprises individual memory cells that stores both the compressed user data and information in more than two states, thereby to store more than one bit of said user data and information per cell. 
   
   
       17 . The assembly of  claim 15 , further comprising at least one personal computer card, the mother card simultaneously connected with said at least one personal computer card and said memory card. 
   
   
       18 . The assembly of  claim 17 , said mother card comprising a plurality of receptacles integrally formed with the mother card, said plurality of receptacles shaped to receive said at least one personal computer cards and said memory card simultaneously. 
   
   
       19 . The assembly of  claim 15 , said module comprising a hardware circuit. 
   
   
       20 . The assembly of  claim 15 , where the memory card further comprises a first connector and the mother card further comprises:
 a second connector, whereby the mother card is removably connectable to the memory card by connecting of the first and second connectors to one another, and   wherein the memory card receives from the mother card through the second and first connectors program and erase voltages for respective use in storing data in, and erasing of data from, the array.   
   
   
       21 . The assembly of  claim 20 , wherein the mother card further includes power conversion circuitry for generating the program and erase voltages. 
   
   
       22 . The assembly of  claim 21 , where the mother card further includes a flash system controller circuit.