Semiconductor chip package

Abstract

A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.

1 - 9 . (canceled) 
   
   
       10 . A semiconductor chip package comprising:
 a main board;   a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and   a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate,   wherein the ceramic substrate comprises:   at least one first ground line electrically connecting the conductive shielding layer with the main board;   at least one second ground line electrically connecting the conductive shielding layer with the chip; and   at least one signal line electrically connecting the chip with the main board,   wherein the chip is mounted to the ceramic substrate by wire-bonding.   
   
   
       11 . A semiconductor chip package comprising:
 a main board;   a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and   a shielding substrate stacked on the ceramic substrate and comprising a shielding layer,   wherein the ceramic substrate comprises:   at least one third ground line electrically connecting the shielding layer of the shielding substrate with the main board;   at least one fourth ground line electrically connecting the shielding layer of the shielding substrate with the chip; and   at least one signal line electrically connecting the chip with the main board.   
   
   
       12 . The semiconductor chip package of  claim 11 , wherein the shielding layer comprises:
 an upper conductive shielding layer provided at an upper portion of the shielding substrate;   a lower conductive shielding layer provided at a lower portion of the shielding substrate; and   an intermediate conductive shielding layer disposed between the upper conductive shielding layer and the lower conductive shielding layer.   
   
   
       13 . The semiconductor chip package of  claim 12 , wherein the upper conductive shielding layer and the intermediate conductive shielding layer are connected through a conductive via, and the upper conductive shielding layer and the lower conductive shielding layer are connected through another conductive via. 
   
   
       14 . The semiconductor chip package of  claim 12 , wherein the upper conductive shielding layer covers the ceramic substrate. 
   
   
       15 . The semiconductor chip package of  claim 12 , wherein the upper conductive shielding layer comprises bar-shaped patterns alternately disposed on the ceramic substrate. 
   
   
       16 . The semiconductor chip package of  claim 12 , wherein the upper conductive shielding layer comprises a helical pattern disposed on the ceramic substrate. 
   
   
       17 . The semiconductor chip package of  claim 11 , wherein the third ground line comprises a third conductive via penetrating the ceramic substrate and electrically connecting the shielding layer with a ground terminal of the main board. 
   
   
       18 . The semiconductor chip package of  claim 11 , wherein the fourth ground line comprises a fourth conductive via penetrating the ceramic substrate and electrically connecting the shielding layer with a ground terminal of the chip. 
   
   
       19 . The semiconductor chip package of  claim 11 , wherein the signal line comprises:
 an inner pattern provided in the ceramic substrate and electrically connected with a signal terminal of the chip; and   a signal via provided in the ceramic substrate and electrically connecting the inner pattern with a signal terminal of the main board.   
   
   
       20 . The semiconductor chip package of  claim 11 , wherein the cavity is filled with a resin filler covering and protecting the chip. 
   
   
       21 . The semiconductor chip package of  claim 11 , wherein the chip is mounted to the ceramic substrate by flip-chip bonding. 
   
   
       22 . The semiconductor chip package of  claim 11 , wherein the chip is mounted to the ceramic substrate by wire-bonding.