Apparatus comprising a plurality of arithmetic logic units

Abstract

An arrangement of arithmetic logic units carries out an operation on at least one operand, wherein the operation is determined by operation codes received by the arithmetic logic units. The operation codes and at least one operand are received on a first clock cycle. The result of the operation is output from at least one arithmetic logic unit to at least one further arithmetic logic unit. A result of the plurality of arithmetic logic units is then output on a next clock cycle.

1 . An apparatus, comprising:
 a plurality of arithmetic logic units, wherein each arithmetic logic unit is arranged to carry out an operation determined by one of a plurality of operation codes received by said arithmetic logic units on at least one operand,   wherein said operation codes and said operands are received on a first clock cycle;   the at least one arithmetic logic unit configured to output the result of the operation carried out by that at least one arithmetic logic unit to at least one further arithmetic logic unit;   one of said arithmetic logic units having an output configured to output a result of said operation on the next clock cycle.   
     
     
         2 . The apparatus of  claim 1 , wherein the at least one arithmetic logic unit is a first arithmetic logic unit and the further arithmetic logic unit is a second arithmetic logic unit and the result of the operation carried out by the first arithmetic logic unit forms the at least one operand of the second arithmetic logic unit. 
     
     
         3 . The apparatus of any of  claims 2 , wherein the at least one operand of the first arithmetic logic unit is received from a first control unit. 
     
     
         4 . The apparatus of  claim 3  wherein the first arithmetic logic unit receives a second operand from the first control unit. 
     
     
         5 . The apparatus of  claim 1 , wherein at least some of said plurality of arithmetic logic units are arranged in a cascaded manner such that respective successive arithmetic logic units are arranged to receive an operand from a respective preceding arithmetic logic unit. 
     
     
         6 . The apparatus of  claim 1 , wherein at least some of said plurality of arithmetic logic units are arranged to receive an operand from a common control unit. 
     
     
         7 . The apparatus of  claim 1  wherein at least one of said plurality of arithmetic logic units receives said operation code from a control unit. 
     
     
         8 . The apparatus of  claim 1  wherein at least one arithmetic logic unit is arranged to receive respective operands from at least two other arithmetic logic units. 
     
     
         9 . The apparatus of  claim 1  wherein said operation code received by each respective said plurality of arithmetic logic units is determined by an instruction. 
     
     
         10 . The apparatus of  claim 9 , wherein a plurality of operation codes form a round. 
     
     
         11 . The apparatus of  claim 1  as implemented in an integrated circuit. 
     
     
         12 . The apparatus of  claim 1  as implemented in an encryption/decryption engine. 
     
     
         13 . The apparatus of  claim 1  as implemented in an execute stage of a pipeline. 
     
     
         14 . The apparatus of  claim 1  further comprising at least one of a Fetch stage, Decode stage and Write-back stage of the pipeline. 
     
     
         15 . A method, comprising:
 carrying out on an arrangement of a plurality of arithmetic logic units an operation determined by one of a plurality of operation codes received by said arithmetic logic units on at least one operand;   receiving said plurality of operation codes and said at least one operand on a first clock cycle;   outputting the result of the operation from at least one arithmetic logic unit to at least one further arithmetic logic unit; and   outputting a result of said plurality of arithmetic logic units on the next clock cycle.   
     
     
         16 . An apparatus, comprising:
 an execution stage of a pipeline, comprising:
 an Instruction Decode/Execute block which outputs a plurality of operands and a plurality of opcodes; 
 a first arithmetic logic unit receiving at least a first one of the operands and a first one of the opcodes, the first arithmetic logic unit adapted to perform an arithmetic logic operation on the first one of the operands to output a first output operand; 
 a second arithmetic logic unit receiving at least a second one of the operands, the first output operand and a second one of the opcodes, the second arithmetic logic unit adapted to perform an arithmetic logic operation on the second one of the operands and the first output operand to output a second output operand. 
   
     
     
         17 . The apparatus of  claim 16  wherein the arithmetic logic operation performed by the first arithmetic logic unit is executed on a first clock cycle, and the arithmetic logic operation performed by the second arithmetic logic unit is executed on a second clock cycle following the first clock cycle. 
     
     
         18 . The apparatus of  claim 16 , wherein the execution stage further comprises:
 a third arithmetic logic unit receiving at least a third one of the operands, the second output operand and a third one of the opcodes, the third arithmetic logic unit adapted to perform an arithmetic logic operation on the third one of the operands and the second output operand to output a third output operand.   
     
     
         19 . The apparatus of  claim 18  wherein the arithmetic logic operation performed by the first arithmetic logic unit is executed on a first clock cycle, the arithmetic logic operation performed by the second arithmetic logic unit is executed on a second clock cycle following the first clock cycle; and the arithmetic logic operation performed by the third arithmetic logic unit is executed on a third clock cycle following the second clock cycle. 
     
     
         20 . An apparatus, comprising:
 an execution stage of a pipeline, comprising:
 an Instruction Decode/Execute block which outputs a plurality of operands and a plurality of opcodes; 
 a first arithmetic logic unit receiving at least a first one of the operands and a first one of the opcodes, the first arithmetic logic unit adapted to perform an arithmetic logic operation on the first one of the operands to output a first output operand; 
 a second arithmetic logic unit receiving at least a second one of the operands and a second one of the opcodes, the second arithmetic logic unit adapted to perform an arithmetic logic operation on the second one of the operands to output a second output operand. 
   
     
     
         21 . The apparatus of  claim 20  wherein the arithmetic logic operations performed by the first and second arithmetic logic unit are executed on a first clock cycle. 
     
     
         22 . The apparatus of  claim 20 , wherein the execution stage further comprises:
 a third arithmetic logic unit receiving the first and second output operands and a third one of the opcodes, the third arithmetic logic unit adapted to perform an arithmetic logic operation on the first and second output operands to output a third output operand.   
     
     
         23 . The apparatus of  claim 22  wherein the arithmetic logic operations performed by the first and second arithmetic logic unit are executed on a first clock cycle, and the arithmetic logic operation performed by the third arithmetic logic unit is executed on a second clock cycle following the first clock cycle.