Method for reducing supply voltage drop in digital circuit block and related layout architecture

Abstract

A method for reducing a supply voltage drop in a digital circuit block, where the digital circuit block includes a first conducting segment coupled to a first supply voltage, a second conducting segment coupled to a second supply voltage, and a digital logic coupled between the first conducting segment and the second conducting segment, the method including: constructing a third conducting segment connected to the first conducting segment and not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer; and constructing a fourth conducting segment electrically connected to the second conducting segment and not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at a second conducting layer, and whereby a capacitive element is formed between the first portion and the second portion.

1 . A method for reducing a supply voltage drop in a digital circuit block, the digital circuit block comprising a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, the method comprising:
 constructing a third conducting segment having a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer, and an dielectric layer is between the first conducting layer and a second conducting layer; and   constructing a fourth conducting segment having a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the second conducting layer, and whereby a first capacitive element is formed between the first portion and the second portion.   
     
     
         2 . The method of  claim 1 , wherein the third conducting segment is further configured to have a third portion located at the second conducting layer, whereby a second capacitive element is formed between the second portion and the third portion. 
     
     
         3 . The method of  claim 1 , wherein one of the first supply voltage and the second supply voltage is a power supply voltage, and the other of the first supply voltage and the second supply voltage is a ground voltage. 
     
     
         4 . The method of  claim 1 , wherein the second conducting layer is adjacent to the first conducting layer. 
     
     
         5 . The method of  claim 1 , wherein the dielectric layer is an oxide layer. 
     
     
         6 . A method for reducing a supply voltage drop in a digital circuit block, the digital circuit block comprising a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, the method comprising:
 constructing a third conducting segment having a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a conducting layer; and   constructing a fourth conducting segment having a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the conducting layer, whereby a capacitive element is formed between the first portion and the second portion.   
     
     
         7 . The method of  claim 6 , wherein one of the first supply voltage and the second supply voltage is a power supply voltage, and the other of the first supply voltage and the second supply voltage is a ground voltage. 
     
     
         8 . A layout architecture for reducing a supply voltage drop in a digital circuit block, the digital circuit block comprising a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, the layout architecture comprising:
 a third conducting segment, having a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer, and a dielectric layer is between the first conducting layer and a second conducting layer; and   a fourth conducting segment, having a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the second conducting layer, and whereby a first capacitive element is formed between the first portion and the second portion.   
     
     
         9 . The layout architecture of  claim 8 , wherein the third conducting segment is further configured to have a third portion located at the second conducting layer, whereby a second capacitive element is formed between the second portion and the third portion. 
     
     
         10 . The layout architecture of  claim 8 , wherein one of the first supply voltage and the second supply voltage is a power supply voltage, and the other of the first supply voltage and the second supply voltage is a ground voltage. 
     
     
         11 . The layout architecture of  claim 8 , wherein the second conducting layer is adjacent to the first conducting layer. 
     
     
         12 . The layout architecture of  claim 8 , wherein the dielectric layer is an oxide layer. 
     
     
         13 . A layout architecture for reducing a supply voltage drop in a digital circuit block, the digital circuit block comprising a first conducting segment having a first end coupled to a first supply voltage, a second conducting segment having a first end coupled to a second supply voltage, and a digital logic coupled between a second end of the first conducting segment and a second end of the second conducting segment, the layout comprising:
 a third conducting segment, having a first end electrically connected to the first conducting segment and a second end not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a conducting layer; and   a fourth conducting segment, having a first end electrically connected to the second conducting segment and a second end not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at the conducting layer, and whereby a capacitive element is formed between the first portion and the second portion.   
     
     
         14 . The layout architecture of  claim 13 , wherein one of the first supply voltage and the second supply voltage is a power supply voltage, and the other of the first supply voltage and the second supply voltage is a ground voltage.