Method to increase strain enhancement with spacerless fet and dual liner process

Abstract

A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.

1 . A semiconductor structure comprising:
 at least one pFET and at least one nFET located on a surface of a semiconductor substrate and separated from each other by an isolation region, wherein at least one of said nFETs or said pFETs is a spacerless PET, each FET including a channel region;   a recrystallized silicide contact located above source/drain diffusion regions of said spacerless FET, said recrystallized silicide contact does not encroach under sidewalls of said spacerless FET; and   a compressive stress inducing liner located around said at least one pFET and a tensile stress inducing liner located around said at least one nFET, wherein at least one of stress inducing liners which is around said spacerless FET is positioned within 30 nm or less from the corresponding channel region.   
   
   
       2 . The semiconductor structure of  claim 1  wherein said semiconductor substrate is a semiconductor-on-insulator substrate or a bulk substrate. 
   
   
       3 . The semiconductor structure of  claim 1  wherein said at least one spacerless FET is a spacerless pFET. 
   
   
       4 . The semiconductor structure of  claim 1  wherein said at least one spacerless FET is a spacerless nFET and a spacerless pFET. 
   
   
       5 . The semiconductor structure of  claim 1  wherein said at least one spacerless FET is void of a wide outer spacer. 
   
   
       6 . The semiconductor structure of  claim 1  wherein said at least one spacerless FET includes a narrow outer spacer having a width from about 5 to about 20 nm. 
   
   
       7 . The semiconductor structure of  claim 1  wherein each FET includes a gate conductor located atop a gate dielectric. 
   
   
       8 . The semiconductor structure of  claim 7  wherein said gate conductor comprises polySi, polySiGe, a metal, a metal nitride, a metal silicide or multilayers thereof. 
   
   
       9 . The semiconductor structure of  claim 8  wherein an upper portion of said polySi or polySiGe gate conductor of said spacerless FET comprises a recrystallized silicide contact. 
   
   
       10 . A semiconductor structure comprising:
 at least one spacerless pFET and at least one nFET located on a surface of a semiconductor substrate and separated from each other by an isolation region, each FET including a channel region;   a recrystallized silicide contact located above source/drain diffusion regions of said spacerless pFET, said recrystallized silicide contact does not encroach under sidewalls of said at least one spacerless pFET;   a compressive stress inducing liner located around said at least one spacerless pFET and a tensile stress inducing liner located around said at least one nFET, wherein said compressive stress inducing liner which is around said spacerless pFET is positioned within 30 nm or less from the corresponding channel region.   
   
   
       11 . The semiconductor structure of  claim 10  wherein said semiconductor substrate is a semiconductor-on-insulator substrate or a bulk substrate. 
   
   
       12 . The semiconductor structure of  claim 10  wherein said at least one spacerless pFET is void of a wide outer spacer. 
   
   
       13 . The semiconductor structure of  claim 10  wherein said at least one spacerless pFET includes a narrow outer spacer having a width from about 5 to about 20 nm. 
   
   
       14 . The semiconductor structure of  claim 10  wherein at least said spacerless pFET includes a gate conductor having an upper surface comprised of a recrystallized silicide contact. 
   
   
       15 . A method of fabricating a semiconductor structure comprising:
 forming a first stress inducing liner and an overlaying hard mask on a structure including at least one spacerless nFET and at least one spacerless pFET, said first stress inducing liner having a first stress type and each FET including a devices channel and a silicided source/drain diffusion contact;   selectively removing said overlying hard mask and said first stress inducing liner from one of said nFETs or pFETs, wherein during removal of said first stress inducing liner from one of said FETs its corresponding silicided source/drain diffusion contact is amorphized;   annealing said structure to recrystallize said amorphized silicided source/drain diffusion contact; and   selectively providing a second stress inducing liner of a second stress type that is different from said first stress type to the spacerless FET in which the first stress inducing liner was previously removed, wherein said first and second stress inducing liners are positioned within 30 nm or less from the corresponding channel region of said spacerless FETs.