Capacitor structure in a semiconductor device

Abstract

A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.

1 . A semiconductor device comprising:
 an integrated circuit formed on a substrate comprising at least one isolator capacitor, the integrated circuit comprising:
 a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate; 
 a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics wherein thickness defining the thick passivation layer is at least a minimum thickness that guarantees isolation and testing for defects is eliminated; and 
 a thick metal layer formed on the thick passivation layer, the at least one isolator capacitor formed comprising the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator; and 
 the at least one isolator capacitor comprising the thick passivation layer and the thick metal layer. 
   
   
   
       2 . The device according to  claim 1  further comprising:
 the thick metal layer comprising a redistribution layer (RDL); and   a metal via formed beneath the RDL that locally replaces the thick passivation layer under the RDL.   
   
   
       3 . The device according to  claim 1  further comprising:
 at least one metal via configured to prevent local deposition of materials with unfavorable breakdown voltages.   
   
   
       4 . The device according to  claim 1  further comprising:
 a metal via; and   a selected metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics underlying the metal via and extending laterally wherein lateral extension of the metal via overlaps the predetermined metal layer.   
   
   
       5 . The device according to  claim 1  wherein:
 the thick metal layer is functional as a first plate and a selected metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics are functional as a second plate in an isolation capacitor; and   the first plate and the second plate are arranged as substantially parallel planes extending laterally with an overlap selected to compensate for dielectric leakage and fringe fields from creating voltage gradients.   
   
   
       6 . The device according to  claim 5  further comprising:
 the first plate and the second plate formed with rounded or oblique angles wherein electric fields and/or voltage gradients are reduced or minimized.   
   
   
       7 . The device according to  claim 1  further comprising:
 a plurality of metal layers distributed within silicate glass dielectric layers, separated by thin silicon nitride layers and overlying inter-layer dielectric layers;   the thick metal layer comprising a redistribution layer (RDL);   the thick passivation layer comprising an undoped silicate glass (USG) layer.   
   
   
       8 . The device according to  claim 1  wherein:
 the at least one isolator capacitor comprises the thick passivation layer functional as an insulator wherein thickness of the passivation layer is selected to reduce parasitic capacitance and improve high-speed operation of the interface.   
   
   
       9 . The device according to  claim 1  wherein:
 the at least one isolator capacitor comprises the thick passivation layer functional as an insulator wherein thickness of the passivation layer is selected to reduce capacitor size of the at least one isolator capacitor.   
   
   
       10 . The device according to  claim 1  further comprising:
 the integrated circuit configured wherein the substrate, the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics, the thick passivation layer, and the thick metal layer are formed by standard processing according to Institute of Electrical and Electronics Engineers (IEEE) 802.3-2007.   
   
   
       11 . The device according to  claim 1  further comprising:
 the integrated circuit configured wherein thickness of the thick passivation layer is selected to be larger than for standard processing according to Institute of Electrical and Electronics Engineers (IEEE) 802.3-2007 and impact of oxide defects are reduced.   
   
   
       12 . The device according to  claim 1  further comprising:
 the integrated circuit divided into at least two dies arranged across an isolation barrier wherein capacitors respectively formed on separate dies are configured with a reduced ratio of parasitic capacitance to primary capacitance.   
   
   
       13 . The device according to  claim 1  further comprising:
 the integrated circuit divided into at least two dies wherein adjacent dies from the integrated circuit are arranged across an isolation barrier and capacitors are matched.   
   
   
       14 . The device according to  claim 1  wherein:
 the integrated circuit comprises a signal interface and the at least one isolator capacitor.   
   
   
       15 . The device according to  claim 1  further comprising:
 the integrated circuit divided into at least two dies wherein adjacent dies from the integrated circuit are arranged across an isolation barrier and parts of a capacitor on different dies are formed from the same wafer and matched.   
   
   
       16 . A semiconductor device comprising:
 an integrated circuit formed on a substrate and divided into at least two dies arranged across an isolation barrier, the integrated circuit comprising:
 a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate; 
 a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics; 
 a thick metal layer formed on the thick passivation layer; and 
 a plurality of isolator capacitors respectively formed of the thick metal layer and at least one metal layer in the interleaved inter-metal dielectric layers and interlayer dielectrics arranged as substantially parallel planes extending laterally positioned with an overlap amount selected to prevent voltage gradients that result from dielectric leakage and fringe fields, the plurality of isolator capacitors formed on separate dies from a single wafer. 
   
   
   
       17 . The device according to  claim 16  wherein:
 the thick metal layer and at least one metal layer in the interleaved inter-metal dielectric layers and interlayer dielectrics are formed with rounded or oblique angles wherein electric fields and/or voltage gradients are reduced or minimized.   
   
   
       18 . The device according to  claim 16  further comprising:
 the thick metal layer comprising a redistribution layer (RDL) wherein thickness defining the thick passivation layer is at least a minimum thickness that guarantees isolation and testing for defects is eliminated;   at least one metal via formed beneath the RDL preventing deposition of passivation and formed to prevent deposition of materials with unfavorable breakdown voltages; and   a predetermined metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics underlying the metal via and extending laterally wherein lateral extension of the metal via overlaps the predetermined metal layer.   
   
   
       19 . The device according to  claim 16  further comprising:
 the integrated circuit configured wherein the substrate, the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics, the thick passivation layer, and the thick metal layer are formed by standard processing according to Institute of Electrical and Electronics Engineers (IEEE) 802.3-2007.   
   
   
       20 . The device according to  claim 16  further comprising:
 the integrated circuit configured wherein thickness of the thick passivation layer is selected to be larger than for standard processing according to Institute of Electrical and Electronics Engineers (IEEE) 802.3-2007 and oxide defects are reduced.   
   
   
       21 . A method for forming a semiconductor device comprising:
 specifying thickness of a thick passivation layer to be greater than thickness required for isolation so that testing for defects is eliminated;   forming a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics on a substrate;   forming a thick passivation layer on the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics;   forming a thick metal layer on the thick passivation layer;   forming an integrated circuit on the substrate comprising a signal interface with at least one isolator capacitor; and   forming the at least one isolator capacitor comprising the thick passivation layer as an insulator.   
   
   
       22 . The method according to  claim 21  further comprising:
 selecting thickness of the passivation layer to reduce parasitic capacitance;   forming the thick metal layer as a redistribution layer (RDL); and   forming a metal via beneath the RDL.   
   
   
       23 . The method according to  claim 21  further comprising:
 forming a metal via beneath the thick metal layer;   forming at least one metal layer in selected layer(s) of the interleaved inter-metal dielectric layers and interlayer dielectrics plurality underlying the metal via and extending laterally wherein lateral extension of the metal via overlaps a predetermined metal layer; and   forming the at least one isolation capacitor as the thick metal layer functional as a first plate and a predetermined metal layer in the interleaved inter-metal dielectric layer and interlayer dielectric plurality functional as a second plate, the first plate and second plate separated by the thick passivation layer; and   arranging the first plate and the second plate as substantially parallel planes extending laterally with an overlap selected to compensate for dielectric leakage and fringe fields from creating voltage gradients.   
   
   
       24 . The method according to  claim 21  further comprising:
 forming at least one metal via to prevent local deposition of materials with unfavorable breakdown voltages; and   forming the first plate and the second plate with rounded or oblique angles wherein electric fields and/or voltage gradients are reduced or minimized.   
   
   
       25 . The method according to  claim 21  further comprising:
 forming the substrate, the plurality of metal layers, the thick passivation layer, and the thick metal layer by standard processing according to Institute of Electrical and Electronics Engineers (IEEE) 802.3-2007; and   forming the thick passivation layer with thickness selected to be larger than for standard processing according to Institute of Electrical and Electronics Engineers (IEEE) 802.3-2007 wherein oxide defects are reduced.