Dual Layer Printed Circuit Board

Abstract

Memory systems are disclosed which are comprised of a two or dual layer printed circuit board. Attached to the top layer of the dual layer printed circuit board are a memory chip and a memory controller with aligned, optimistic pin outs that optimized signal integrity layouts between certain high speed pins in a single layer. A set of high speed lines, including the data lines, that do not include any vias connect certain of the pins of the memory controller to certain of the pins of the memory chip. The high speed lines are covered by a sub-PCB that includes a copper lay that extends a ground or electrical plane above the top layer of the dual layer printed circuit board.

1 . A circuit board assembly for use in a memory system including a controller and a memory chip comprising:
 a two layer printed circuit board (PCB) comprising a top layer and a bottom layer, wherein the top layer comprises a reserved memory chip space and a reserved controller space;   a first set of no via data lines that connect a first set of points of the reserved controller space to a first set of points of the reserved memory chip space; and   a set of secondary lines that connect a second set of points of the reserved controller space to a second set of points of the reserved memory chip space; and   one or more sub-PCBs;   wherein each of the one or more sub-PCBs comprises an electrical plane;   the first set of no via data lines and the set of secondary lines are substantially covered by the one or more sub-PCBs; and   a first set of points of the controller and a first set of points of the memory chip are optimistically laid out to allow substantially direct connections from the first set of points of the controller to the second set of points of the memory chip along the set of no via data lines.   
     
     
         2 . The memory system of  claim 1  wherein the top layer further comprises
 a second reserved memory chip space.   
     
     
         3 . The memory system of  claim 2  further comprising:
 a second set of no via data lines that connect a third set of points of the reserved controller space to a first set of points of the second reserved memory chip space; and   wherein the set of secondary lines connects the second set of points of the controller to a second set of points of the second reserved memory chip space; and   the second set of no via data lines are substantially covered by the one or more sub-PCBs.   
     
     
         4 . The memory system of  claim 3  wherein a gap between each of the one or more sub-PCBs and a surface of the bottom layer over the set of secondary lines is less than about 1.5 mils. 
     
     
         5 . The memory system of  claim 1  wherein a gap between each of the one or more sub-PCBs and a surface of the top layer over the first set of no via data lines and the set of secondary lines is less than about 0.7 mils. 
     
     
         6 . The memory system of  claim 5  wherein a gap between each of the one or more sub-PCBs and a surface of the bottom layer over the set of secondary lines is less than about 0.7 mils. 
     
     
         7 . The memory system of  claim 1  wherein a portion of the secondary set of lines on the top layer and a portion of the secondary set of lines on the bottom layer generally form a T shape. 
     
     
         8 . The memory system of  claim 1  wherein a portion of the secondary set of lines on the top layer and a portion of the secondary set of lines on the bottom layer generally form a U shape. 
     
     
         9 . A DDR2 SDRAM memory system comprising:
 a two layer PCB comprising a top layer and a bottom layer;   a controller attached to the top layer of the two layer PCB;   a memory chip attached to the top layer of the two layer PCB;   a first set of no via data lines that connect a first set of pins of the controller to a first set of pins of the memory chip;   a set of secondary lines that connect a second set of pins of the controller to a second set of pins of the memory chip; and   one or more sub-PCBs;   wherein each of the one or more sub-PCBs comprises an electrical plane;   the memory chip operates at a frequency of about 400 MHz or above;   the first set of no via data lines and the set of secondary lines are substantially covered by the one or more sub-PCBs;   the first set of pins of the controller and the first set of pins of the memory chip are optimistically laid out to allow substantially direct connections from the first set of pins to the second set of pins along the set of no via data lines.   
     
     
         10 . The DDR2 SDRAM memory system of  claim 9  further comprising:
 a second memory chip attached to the top layer of the two layer printed circuit board (PCB); and   a second set of no via data lines that connect a third set of pins of the controller to a first set of pins of the second memory chip;   wherein the set of secondary lines connects the second set of pins of the controller to a second set of pins of the second memory chip; and   the second set of no via data lines are substantially covered by the one or more sub-PCBs.   
     
     
         11 . The DDR2 SDRAM memory system of  claim 10  wherein a gap between each of the one or more sub-PCBs and a surface of the top layer over the first set of no via data lines, the second set of no via data lines and the set of secondary lines is less than about 1.5 mils. 
     
     
         12 . The DDR2 SDRAM memory system of  claim 11  wherein a gap between each of the one or more sub-PCBs and a surface of the bottom layer over the set of secondary lines is less than about 1.5 mils. 
     
     
         13 . The DDR2 SDRAM memory system of  claim 10  wherein a gap between each of the one or more sub-PCBs and a surface of the top layer over the first set of no via data lines, the second set of no via data lines and the set of secondary lines is less than about 0.7 mils. 
     
     
         14 . The DDR2 SDRAM memory system of  claim 13  wherein a gap between each of the one or more sub-PCBs and a surface of the bottom layer over the set of secondary lines is less than about 0.7 mils. 
     
     
         15 . A method of creating a DDR2 SDRAM memory system comprising:
 providing a DDR2 SDRAM memory controller and a DDR2 SDRAM memory chip such that a first set of pins of the DDR2 SDRAM memory controller and a first set of pins of the SDRAM memory chip are optimistically laid out;   providing a two layer printed circuit board (PCB) with a first set of traces running along a first layer of the two layer board for connecting the first set of pins of the DDR2 SDRAM memory controller to the first set of pins of the SDRAM memory chip;   attaching the DDR2 SDRAM memory controller and the DDR2 SDRAM memory chip to the first set of traces on the first layer of the two layer board; and   substantially covering the first set of traces with an electrical plane.   
     
     
         16 . The method of  claim 15  further comprising creating the DDR2 SDRAM memory chip to operate at a frequency greater than about 400 MHz. 
     
     
         17 . The method of  claim 15  wherein the electrical plane is a ground plane 
     
     
         18 . The method of  claim 15  wherein the electrical plane is a power plane. 
     
     
         19 . A method of connecting a first set of pins of a memory controller and a first set of pins of a memory chip, wherein the memory chip operates with a clock frequency above about 400 MHz, comprising:
 creating a two layer printed circuit board (PCB) with a first set of traces running along a first layer of the PCB for connecting the first set of pins of the memory controller to the first set of pins of the memory chip;   attaching the memory controller and the memory chip to the first set of traces on the first layer of the two layer board; and   substantially covering the first set of traces with a sub-PCB.   
     
     
         20 . The method of  claim 19  further comprising creating the memory chip to operate at a frequency greater than about 400 MHz. 
     
     
         21 . A DDR2 SDRAM memory system comprising:
 a two layer PCB comprising a top layer and a bottom layer;   a controller attached to the top layer of the two layer PCB;   a memory chip attached to the top layer of the two layer PCB;   a first set of no via data lines that connect a first set of pins of the controller to a first set of pins of the memory chip; and   a set of secondary lines that connect a second set of pins of the controller to a second set of pins of the memory chip; and   one or more sub-PCBs;   wherein each of the one or more sub-PCBs comprises an electrical plane;   the first set of no via data lines and the set of secondary lines are substantially covered by the one or more sub-PCBs;   the first set of pins of the controller and the first set of pins of the memory chip are optimistically laid out to allow substantially direct connections from the first set of pins to the second set of pins along the set of no via data lines.   
     
     
         22 . The DDR2 SDRAM memory system of  claim 21  further comprising:
 a second memory chip attached to the top layer of the two layer PCB; and   a second set of no via data lines that connect a third set of pins of the controller to a first set of pins of the second memory chip;   wherein the set of secondary lines connects the second set of pins of the controller to a second set of pins of the second memory chip; and   the second set of no via data lines are substantially covered by the one or more sub-PCBs.   
     
     
         23 . The DDR2 SDRAM memory system of  claim 21  wherein a gap between each of the one or more sub-PCBs and a surface of the top layer over the first set of no via data lines and the set of secondary lines is less than about 1.5 mils. 
     
     
         24 . The DDR2 SDRAM memory system of  claim 23  wherein a gap between each of the one or more sub-PCBs and a surface of the bottom layer over the set of secondary lines is less than about 1.5 mils. 
     
     
         25 . The DDR2 SDRAM memory system of  claim 21  wherein a gap between each of the one or more sub-PCBs and a surface of the top layer over the first set of no via data lines and the set of secondary lines is less than about 0.7 mils. 
     
     
         26 . The DDR2 SDRAM memory system of  claim 25  wherein a gap between each of the one or more sub-PCBs and a surface of the bottom layer over the set of secondary lines is less than about 0.7 mils. 
     
     
         27 . The DDR2 SDRAM memory system of  claim 21  wherein the memory chip operates at a clock frequency above about 200 MHz. 
     
     
         28 . The DDR2 SDRAM memory system of  claim 21  wherein the memory chip operates at a clock frequency above about 400 MHz.