Thin Film Transistor Array Panel and Manufacturing Method Thereof

Abstract

A thin film transistor array panel is provided, which includes: a substrate; a first polysilicon member that is formed on the substrate and includes an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region; a first insulator formed on the first polysilicon member and having an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region; and a first electrode formed on the first insulator and having an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region.

1 - 19 . (canceled) 
   
   
       20 . A thin film transistor comprising:
 a polysilicon member comprising:   an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region;   a first insulator formed on the polysilicon member;   a first electrode formed on the first insulator; and   a second insulator disposed between the polysilicon member and the first insulator, wherein, edges of the first insulator and the second insulator are disposed between an edge of the first electrode and an edge of the polysilicon member, and the at least one second extrinsic region is substantially covered by the second insulator.   
   
   
       21 . The thin film transistor of  claim 20 , wherein the second insulator has an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region, and the first electrode has an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region. 
   
   
       22 . The thin film transistor of  claim 21 , wherein the at least one first extrinsic region comprises a pair of source and drain regions disposed opposite each other with respect to the intrinsic region and the at least one second extrinsic region comprises a pair of lightly doped regions disposed opposite each other with respect to the intrinsic region. 
   
   
       23 . A thin film transistor array panel comprising:
 an insulating substrate   a first polysilicon member formed on the insulating substrate, and comprising:   an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region;   a first insulator formed on the first polysilicon member;   a first electrode formed on the first insulator; and   a second insulator disposed between the first polysilicon member and the first insulator, wherein, edges of the first insulator and the second insulator are disposed between an edge of the first electrode and an edge of the polysilicon member, and the at least one second extrinsic region is substantially covered by the second insulator.   
   
   
       24 . The thin film transistor array panel of  claim 23 , wherein the second insulator has an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region, and the first electrode has an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region. 
   
   
       25 . The thin film transistor array panel of  claim 23 , wherein the at least one second extrinsic region has a thickness smaller than the at least one first extrinsic region wherein the direction of the thickness is perpendicular to a planar direction of the insulating substrate. 
   
   
       26 . The thin film transistor array panel of  claim 25 , wherein the at least one first extrinsic region comprises a pair of source and drain regions disposed opposite each other with respect to the intrinsic region and the at least one second extrinsic region comprises a pair of lightly doped regions disposed opposite each other with respect to the intrinsic region. 
   
   
       27 . A method of manufacturing a thin film transistor array panel comprising:
 forming a polysilicon member on an insulating substrate;   depositing a gate insulating film;   depositing a conductive film;   forming a photoresist;   patterning the conductive film by using the photoresist as an etch mask to form a gate electrode;   patterning the gate insulating film by using the photoresist as an etch mask to form a gate insulator;   removing the photoresist;   forming source and drain regions having a first impurity concentration by introducing impurity into the polysilicon member using the gate insulator as a mask after removing the photoresist; and   forming lightly doped regions having a second impurity concentration lower than the first impurity concentration by introducing impurity into the polysilicon member using the gate electrode as a mask after removing the photoresist,   wherein the conductive film is patterned to form the gate electrode and the gate insulating film is patterned to form the gate insulator such that an edge of the formed gate electrode is narrower than the gate insulator, the thickness of the lightly doped regions is thinner than the thickness of the source and drain regions, and the direction of thicknesses is perpendicular to the insulating substrate, and   wherein the introduction of the impurity for the formation of lightly doped regions is performed using energy higher than the introduction of the impurity for the formation of source and drain regions.   
   
   
       28 . The method of manufacturing a thin film transistor array panel of  claim 27 , wherein, the depositing a gate insulating film comprises:
 depositing a first gate insulating film on the polysilicon member; and   depositing a second gate insulating film on the first gate insulating film.   
   
   
       29 . The method of manufacturing a thin film transistor array panel of  claim 28 , wherein, the patterning the conductive film comprises an isotropic etching of the conductive film. 
   
   
       30 . The method of manufacturing a thin film transistor array panel of  claim 28 , wherein, the patterning the gate insulating film comprises an anisotropic etching of at least one of the first gate insulating film and the second gate insulating film.