Method of forming a semiconductor structure

Abstract

A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

1 . A method of forming a semiconductor structure, comprising:
 providing a semiconductor substrate;   forming a feature over said substrate, said feature being substantially homogeneous in a lateral direction;   performing a first ion implantation process adapted to introduce first dopant ions into at least one portion of said substrate adjacent said feature;   reducing a length of said feature in said lateral direction;   after said reduction of said length of said feature, performing a second ion implantation process adapted to introduce second dopant ions into at least one portion of said substrate adjacent said feature   forming a first material layer over said semiconductor structure after said second ion implantation process;   performing a first planarization process on said first material layer to expose said feature;   removing said feature to form an opening in said first material layer; and   after removing said feature, forming a second material layer over said semiconductor structure.   
     
     
         2 . (canceled) 
     
     
         3 . The method of  claim 1 , wherein a height of said feature in a height direction substantially perpendicular to said lateral direction is reduced during said reduction of said length of said feature. 
     
     
         4 . The method of  claim 1 , wherein said feature comprises a top surface and a side surface, and wherein said reduction of said length of said feature comprises performing an etching process wherein at least one of said side surface and said top surface is exposed to an etchant adapted to remove a material of said feature. 
     
     
         5 . The method of  claim 4 , wherein both said side surface and said top surface are exposed to said etchant to reduce a height of said feature in a height direction substantially perpendicular to said lateral direction. 
     
     
         6 . (canceled) 
     
     
         7 . The method of  claim 4 , wherein said etching process is an anisotropic etching process. 
     
     
         8 . The method of  claim 4 , wherein said feature comprises a mask layer, said mask layer being adapted to protect said top surface of said feature from being affected by said etchant during said etching process. 
     
     
         9 . (canceled) 
     
     
         10 . The method of  claim 1 , further comprising removing portions of said second material layer outside said opening. 
     
     
         11 . The method of  claim 1 , wherein said second material layer comprises an electrically conductive material. 
     
     
         12 . The method of  claim 11 , further comprising forming a layer of a dielectric material below said second material layer. 
     
     
         13 . The method of  claim 10 , wherein removing said portions of said second material layers outside said opening comprises performing a second planarization process. 
     
     
         14 . The method of  claim 1 , wherein an implantation depth of said second dopant ions is smaller than an implantation depth of said first dopant ions. 
     
     
         15 .- 20 . (canceled) 
     
     
         21 . A method of forming a gate electrode structure, comprising:
 forming a placeholder element over a semiconductor substrate, said placeholder element having a first length in a lateral direction;   forming source/drain regions in said semiconductor substrate adjacent said placeholder element based on said first length;   reducing a length of said placeholder element to a second length in said lateral direction, wherein reducing said length comprises performing a first etching process;   forming extended source/drain regions in said semiconductor substrate adjacent said placeholder element based on said second length;   forming a first material layer over said semiconductor structure after forming said extended source/drain regions, wherein a thickness of said first material layer is greater than a height of said placeholder element;   performing a first planarization process to expose said placeholder element;   removing said placeholder element to form an opening in said first material layer, wherein removing said placeholder element comprises performing a second etching process;   after removing said placeholder element, forming a layer of gate insulation material above said semiconductor substrate;   forming a layer of gate electrode material above said gate insulation material; and   performing a second planarization process to remove excess portions of said gate insulation material and gate electrode material outside of said opening.   
     
     
         22 . The method of  claim 21 , wherein said first material layer comprises a dielectric material. 
     
     
         23 . The method of  claim 22 , wherein said dielectric material comprises an intrinsic stress. 
     
     
         24 . The method of  claim 21 , further comprising removing said first material layer after performing said second planarization process, wherein removing said first material layer comprises performing a third etching process. 
     
     
         25 . The method of  claim 21 , further comprising forming a mask layer above said placeholder element prior to performing said first etching process.