Speculative Region: Hardware Support for Selective Transactional Memory Access Annotation Using Instruction Prefix

Abstract

A computer system and method is disclosed for executing selectively annotated transactional regions. The system is configured to determine whether an instruction within a plurality of instructions in a transactional region includes a given prefix. The prefix indicates that one or more memory operations performed by the processor to complete the instruction are to be executed as part of an atomic transaction. The atomic transaction can include one or more other memory operations performed by the processor to complete one or more others of the plurality of instructions in the transactional region.

1 . An apparatus, comprising:
 a computer processor configured to determine whether an instruction within a plurality of instructions in a transactional region of code includes a prefix indicating that one or more memory operations performed by the computer processor to complete the instruction are to be executed as part of an atomic transaction that includes memory operations performed by the computer processor to complete at least one other of the plurality of instructions.   
     
     
         2 . The apparatus of  claim 1 , wherein the computer processor is further configured to determine that at least some other of the plurality of instructions do not include the prefix and in response, to execute those instructions non-atomically. 
     
     
         3 . The apparatus of  claim 1 , wherein the one or more memory operations performed by the computer processor to complete the instruction are implicit memory operation of the instruction. 
     
     
         4 . The apparatus of  claim 1 , wherein execution of the one or more memory operations includes buffering versioning data for the instruction in a data cache of the processor. 
     
     
         5 . The apparatus of  claim 1 , wherein the computer processor comprises a decoder unit and at least one execution unit, wherein the decoder is configured to determine that the instruction includes the prefix and to send the instruction to the at least one execution unit with an indication that the instruction is speculative. 
     
     
         6 . The apparatus of  claim 1 , wherein the computer processor is configured to execute all of the plurality of instructions as speculative instructions in response to an opcode portion of the instruction indicating the start of the transactional region of code. 
     
     
         7 . The apparatus of  claim 1 , wherein at least one other of the plurality of instructions also includes the prefix indicating that one or more memory operations performed by the computer processor to complete the at least one other instruction are to be executed as part of the atomic transaction. 
     
     
         8 . The apparatus of  claim 1 , wherein the computer processor is configured to detect an abort condition while executing the transactional region of code, and, in response thereto, to abort execution of the transactional region of code, at least by undoing modifications to values stored in memory as a result of executing one or more speculative instructions within the plurality of instructions without undoing modifications to one or more other values stored in memory as a result of executing one or more non-speculative instructions within the plurality of instructions. 
     
     
         9 . A method comprising:
 a computer processor detecting a transactional region of code having a plurality of instructions; and   the computer processor determining that an instruction within the transactional region includes a prefix indicating that the instruction is to be executed as part of an atomic memory transaction that includes one or more other instructions in the transactional region.   
     
     
         10 . The method of  claim 9 , further comprising:
 the computer processor determining that at least some other of the plurality of instructions are not to be executed as part of the atomic memory transaction; and   executing the at least some other instructions non-atomically.   
     
     
         11 . The method of  claim 9 , further comprising:
 determining that execution of the instruction includes at least one implicit memory operation and in response, executing the at least one implicit memory operation as part of the atomic memory transaction.   
     
     
         12 . The method of  claim 9 , further comprising: executing the instruction as part of the atomic memory transaction, wherein said executing includes buffering versioning data for the instruction. 
     
     
         13 . The method of  claim 9 , wherein the instruction indicates the start of the transactional region of code. 
     
     
         14 . The method of  claim 13 , further comprising: in response to the instruction indicating the start of the transactional region of code, determining that all of the plurality of instructions are to be executed as part of the atomic memory transaction. 
     
     
         15 . The method of  claim 9 , wherein the one or more other instructions in the transactional region included in the atomic transaction also include the prefix. 
     
     
         16 . The method of  claim 9 , further comprising:
 attempting to execute the atomic memory transaction, wherein said attempting includes:
 detecting an abort condition; and 
 in response to detecting the abort condition, aborting execution of the transactional region of code at least by undoing memory effects of one or more instructions within the transactional region that include the prefix without undoing memory effects of one or more instructions within the transactional region that do not include the prefix; and 
   reattempting to execute the transactional region of code.   
     
     
         17 . A computer-readable storage medium having stored thereon program instructions executable by a processor, wherein the program instructions comprise:
 a plurality of instructions in a transactional region of code, the instructions executable by the processor in a transactional mode of execution;   wherein at least some of the instructions in the transactional region include a prefix that indicates to the processor that memory operations performed by the processor as part of executing the instructions that include the prefix are to be performed as a single atomic memory transaction.   
     
     
         18 . The computer-readable storage medium of  claim 17 , wherein the plurality of instructions include:
 a transaction-initiating instruction executable by the processor to begin the transactional mode of execution;   a transaction-terminating instruction executable by the processor to exit the transactional mode of execution;   wherein the processor is configured to determine that the transaction-initiating instruction includes the prefix and in response, to execute all memory operations performed as part of executing the plurality of instructions in the transactional region as part of the atomic memory transaction.   
     
     
         19 . The computer-readable storage medium of  claim 17 , wherein the plurality of instructions include:
 a transaction-initiating instruction executable by the processor to begin the transactional mode of execution;   a transaction-terminating instruction executable by the processor to exit the transactional mode of execution;   intermediate instructions appearing between the transaction-initiating instruction and transaction-terminating instruction in program execution order;   wherein each of two or more of the intermediate instructions includes a prefix indicating to the processor that the two or more intermediate instructions are to be executed together as part of the atomic memory transaction, and wherein at least one of the intermediate instructions does not include the prefix.   
     
     
         20 . The computer-readable storage medium of  claim 17 , wherein the transaction-initiating instruction includes an operand indicating a memory address to which execution should jump in the event that an attempt to atomically execute two or more intermediate instruction appearing between the transaction-initiating instruction and transaction-terminating instruction in program execution order is aborted. 
     
     
         21 . A computer readable storage medium comprising a data structure that is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:
 a computer processor configured to determine whether an instruction within a plurality of instructions in a transactional region of code includes a prefix indicating that the instruction is to be executed speculatively within a single atomic memory transaction.