US2010205477A1PendingUtilityA1
Memory Handling Techniques To Facilitate Debugging
Assignee: SONY COMP ENTERTAINTMENT INCPriority: Jun 22, 2007Filed: Mar 17, 2010Published: Aug 12, 2010
Est. expiryJun 22, 2027(~0.9 yrs left)· nominal 20-yr term from priority
Inventors:Brian Watson
G06F 11/3636
44
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Claims
Abstract
A method for debugging includes interacting with a memory management component to force an interrupt upon access to one or more memory locations during software execution, and in response to the forced interrupt, saving information regarding the execution of the software, and interacting with the memory management component to disable the interrupt upon access to the one or more memory locations during software execution.
Claims
exact text as granted — not AI-modified1 . A method for automatic recovery from a fatal error in a computer system, the method comprising:
periodically forcing interrupts in a computer system; in response to a forced interrupt, capturing information regarding the operating state of the computer system; detecting an error during operation of the computer system; and in response to a detected error, invoking an automatic recovery process that places the computer system in a recovered operating state using the captured information.
2 . The method of claim 1 , wherein a memory management component of the computer system periodically forces interrupts.
3 . The method of claim 1 , wherein capturing information regarding the operating state of the computer system includes storing contents of one or more registers.
4 . The method of claim 1 , wherein capturing information regarding the operating state of the computer system includes storing contents of one or more memory locations.
5 . The method of claim 1 , wherein capturing information regarding the operating state of the computer system includes storing user-selected state information.
6 . The method of claim 1 , wherein the detected error is a segmentation violation.
7 . The method of claim 1 , wherein the detected error is an illegal instruction.
8 . The method of claim 1 , wherein the detected error is a privilege error.
9 . A non-transient computer-readable medium comprising software operable to enable automatic recovery from a fatal error in a computer system, the software comprising:
instructions to periodically force interrupts in a computer system; instructions to capture information regarding the operating state of the computer system in response to a forced interrupt; and instructions to invoke an automatic recovery process in response to an error detected during operation of the computer system, the automatic recovery process using the captured information to place the computer system in a recovered operating state.
10 . A system, comprising:
a memory; and a processor coupled to the memory, the processor operable to execute a series of instructions, wherein a processor interrupt is periodically invoked and system state information is captured in response to an invoked processor interrupt, and wherein the system is operable to recover from a fatal error by restoring the captured system state information in response to the fatal error.
11 . The system of claim 10 , wherein the processor interrupt is invoked in response to an attempted memory access.
12 . The system of claim 10 , wherein the processor interrupt is invoked after an elapsed period of time.
13 . The system of claim 10 , wherein the captured system state information includes contents of one or more registers.
14 . The system of claim 10 , wherein the captured system state information includes contents of one or more memory locations.
15 . The system of claim 10 , wherein the captured system state information includes user-selected state information.
16 . The system of claim 10 , wherein the fatal error is a segmentation violation.
17 . The method of claim 10 , wherein the fatal error is an illegal instruction.
18 . The method of claim 10 , wherein the fatal error is a privilege error.Join the waitlist — get patent alerts
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