Programmable logic devices comprising time multiplexed programmable interconnect

Abstract

A time multiplex logic device is disclosed. The device comprises a single wire segment to couple a plurality of logic outputs to a plurality of logic inputs using a non-overlapping time multiplex sequence of global controls signals. The disclosure includes programmable logic blocks and wire structures that allow wire sharing. Time shared wires offer significant reduction in total wires needed for routing in programmable logic, which accounts for the single largest overhead and cost associated with programmable logic.

1 . A time multiplex look-up-table (LUT) logic circuit of a programmable logic device, the circuit comprising:
 a common input; and   a plurality of control signals comprising a time multiplexing sequence, wherein a said control signal has a non overlapping activation time interval with respect to the other control signals; and   a logic block having a plurality of LUT values and an output, and a plurality of inputs, each input received in true and complement signal pairs, wherein the plurality of inputs couple a said LUT value to the output; and   a plurality of data storage units, each storage unit comprising:
 an input to receive data to store in the storage unit; and 
 two outputs having true and complement data levels of the stored data value in the storage unit, the two outputs coupled to the two signal inputs of a said input of the logic block; and 
   a plurality of access devices, each access device coupled to the common input and the input to a said data storage unit, and a said control signal;   wherein, the common input is coupled to the plurality of data storage units one storage unit at a time by the time multiplexing sequence of the plurality of control signals.   
     
     
         2 . The circuit of  claim 1 , wherein the common input logic state is stored in said plurality of data storage units in a time multiplexed sequence during the activation time intervals of said plurality of control signals. 
     
     
         3 . The circuit of  claim 1 , wherein the common input comprises a valid data setup time and a valid data hold time with respect to one or more of the activation time intervals of the plurality of control signals. 
     
     
         4 . The circuit of  claim 1 , wherein the look-up-table values are stored in user configurable memory elements. 
     
     
         5 . The circuit of  claim 1 , wherein the look up table values are stored in one or more of: a random access memory (RAM) element, or a read only memory (ROM) element. 
     
     
         6 . The circuit of  claim 1 , wherein the common input is coupled to a common interconnect wire, said wire further capable of receiving a plurality of logic signals in the identical time multiplexing sequence of said plurality of control signals. 
     
     
         7 . The circuit of  claim 1 , wherein the storage unit comprises one or more of: a latch, a register, a flip-flop, a FIFO, or any other memory device. 
     
     
         8 . The circuit of  claim 1 , comprising one or more of: a fuse link, an anti-fuse capacitor, an SRAM cell, a DRAM cell, a metal optional link, an EPROM cell, an EEPROM cell, a flash cell, a ferro-electric element, an electro-chemical cell, an electro-magnetic cell, a carbon nano-tube, an optical element, and a magnetic memory element. 
     
     
         9 . A time multiplex interconnect structure of a programmable logic device, the device comprising:
 a plurality of global control signals comprising a time multiplex sequence, wherein a said control signal has a non-overlapping activation time interval with respect to the other control signals; and   a single wire segment to couple a plurality of first outputs to a plurality of first inputs, wherein a said first output is coupled to a said first input during a said non overlapping time interval of a said global control signal; and   a plurality of first logic blocks, each of the first logic blocks comprising a said first output, wherein a said first output can be configured to couple to said single wire segment; and   a plurality of second logic blocks, at least one of the second logic blocks comprising the said plurality of first inputs, wherein the said plurality of first inputs can be configured to couple to said wire segment;   wherein, the single wire segment sequentially couples the plurality of first logic block outputs to the first inputs of said second logic block in said time multiplex sequence.   
     
     
         10 . The device of  claim 9 , wherein only one of the first outputs is coupled to a said first input during a said non-overlapping activation time interval of a said global control signal. 
     
     
         11 . The device of  claim 10 , comprising a data storage unit coupled to the said first input to capture and store the said first output data during said activation time interval. 
     
     
         12 . The device of  claim 9 , wherein each of the first inputs and the first outputs comprises a valid data setup time and a valid data hold time with respect to one or more of the activation time intervals of the plurality of global control signals. 
     
     
         13 . The device of  claim 9 , wherein the first and second logic blocks comprises a plurality of configurable memory elements for a user to program a desired logic function. 
     
     
         14 . The device of  claim 9 , comprising a plurality of wire segments, wherein a said wire segment can be configured to couple to said single wire segment. 
     
     
         15 . The device of  claim 9 , comprising random access memory (RAM) element or a read only memory element (ROM) configurable element. 
     
     
         16 . The device of  claim 9 , wherein a said configurable element of the first device comprises one of a volatile and non-volatile memory element. 
     
     
         17 . The device of  claim 9 , comprising a configuration circuit. 
     
     
         18 . The device of  claim 9 , comprising one or more of: a fuse link, an anti-fuse capacitor, an SRAM cell, a DRAM cell, a metal optional link, an EPROM cell, an EEPROM cell, a flash cell, a ferro-electric element, an electro-chemical cell, an electro-magnetic cell, a carbon nano-tube, an optical element and a magnetic memory element. 
     
     
         19 . A time multiplex logic device comprising:
 a common wire segment; and   a plurality of control signals comprising a time multiplex sequence, wherein a said control signal has a non overlapping activation time interval with respect to the other control signals; and   a plurality of logic outputs coupled to the common wire segment in said time multiplexing sequence by the plurality of control signals; and   a logic block comprising a plurality of inputs coupled to the common wire segment, wherein each input is received and stored in a data storage unit in said time multiplex sequence from a said logic output coupled to said common wire segment;   wherein, the logic block generates a valid logic output in response to the inputs stored in the data storage units at the end of said time multiplex sequence.   
     
     
         20 . The device of  claim 19 , wherein the logic block comprises a plurality of configurable memory elements for a user to program a desired logic function.