Thin-film transistor panel

Abstract

Embodiments of the present disclosure provide a thin-film transistor (TFT) panel structured to prevent the deterioration of image quality due to the luminance change of backlight. According to an embodiment, the TFT panel includes: an insulating substrate; a first gate line and a first data line which are formed on the insulating substrate to be insulated from each other and cross each other; a first subpixel electrode which is formed on the insulating substrate and connected to the first gate line and the first data line by a first TFT; a second subpixel electrode which is formed on the insulating substrate and separated from the first subpixel electrode; a connecting electrode which is directly connected to any one of the first and second subpixel electrodes and capacitively coupled to the other one of the first and second subpixel electrodes; a semiconductor pattern which is formed between the connecting electrode and the insulating substrate; and a light-shielding pattern which is formed between the semiconductor pattern and the insulating substrate, is overlapped by the connecting electrode, and blocks light.

1 . A thin-film transistor (TFT) panel comprising:
 an insulating substrate;   a first gate line and a data line which are formed on the insulating substrate to be insulated from each other and cross each other;   a pixel electrode which is formed on the insulating substrate and connected to the gate line and the data line by a TFT;   a connecting electrode which connects the TFT to the pixel electrode;   a semiconductor pattern which is formed between the connecting electrode and the insulating substrate; and   a light-shielding pattern which is formed between the semiconductor pattern and the insulating substrate, is overlapped by the connecting electrode.   
   
   
       2 . The TFT panel of  claim 1 , wherein the pixel electrode comprise a first subpixel electrode which is formed on the insulating substrate and connected to the first gate line and the first data line by the first TFT and a second subpixel electrode which is formed on the insulating substrate and separated from the first subpixel electrode, and the connecting electrode is directly connected to any one of the first and second subpixel electrodes and capacitively coupled to the other one of the first and second subpixel electrodes. 
   
   
       3 . The TFT panel of  claim 2 , further comprising:
 a second data line which extends parallel to the first data line; and   a second TFT which is connected to the second data line, the first gate line, and the second subpixel electrode.   
   
   
       4 . The TFT panel of  claim 3 , wherein the connecting electrode is a drain electrode of the second TFT which is connected to the second subpixel electrode. 
   
   
       5 . The TFT panel of  claim 4 , further comprising a decoupling electrode between the second subpixel electrode and each of the first and second data lines. 
   
   
       6 . The TFT panel of  claim 5 , wherein at least part of the decoupling electrode is overlapped by the first and second data lines. 
   
   
       7 . The TFT panel of  claim 6 , wherein the semiconductor pattern is formed between the decoupling electrode and the first and second data lines. 
   
   
       8 . The TFT panel of  claim 1 , wherein the light-shielding pattern floats, or a direct current voltage is applied to the light-shielding pattern. 
   
   
       9 . The TFT panel of  claim 2 , further comprising:
 a second gate line which extends parallel to the first gate line;   a second TFT which is connected to the first gate line and the second subpixel electrode;   a storage line which separated from the first gate line and the second gate line;   a control electrode which at least partially overlaps the storage line; and   a third TFT which comprises a gate electrode connected to the second gate line, a source electrode connected to the second subpixel electrode, and a drain electrode connected to the control electrode.   
   
   
       10 . The TFT panel of  claim 9 , wherein the connecting electrode is connected to a drain electrode of the second TFT. 
   
   
       11 . The TFT panel of  claim 9 , wherein the connecting electrode is connected to the source electrode of the third TFT. 
   
   
       12 . The TFT panel of  claim 1 , wherein the light-shielding pattern is approximately 0 to 10 μm wider than the semiconductor pattern. 
   
   
       13 . The TFT panel of  claim 2 , wherein the light-shielding pattern is formed under a connecting electrode which is directly connected to the second subpixel electrode and in a region overlapped by the first subpixel electrode. 
   
   
       14 . The TFT panel of  claim 1 , wherein the light-shielding pattern is formed under the connecting electrode which is directly connected to the first subpixel electrode and in a region overlapped by the second subpixel electrode. 
   
   
       15 . The TFT panel of  claim 1 , wherein the light-shielding pattern is made of the same material as the first gate line. 
   
   
       16 . The TFT panel of  claim 1 , wherein the light-shielding pattern and the first gate line are formed by the same process. 
   
   
       17 . The TFT panel of  claim 2 , wherein the first subpixel electrode surrounds the second subpixel electrode. 
   
   
       18 . The TFT panel of  claim 2 , wherein the second subpixel electrode is V-shaped, and the first subpixel electrode is formed in a region of a pixel excluding a region where the second subpixel electrode is formed. 
   
   
       19 . The TFT panel of  claim 2 , wherein two portions of the second subpixel electrode are adjacent to the first data line, and a portion of the second subpixel electrode meets the second data line. 
   
   
       20 . The panel of  claim 2 , wherein a data voltage having a low gray level is applied to the first subpixel electrode, and a data voltage having a high gray level is applied to the second subpixel electrode. 
   
   
       21 . The panel of  claim 2 , wherein a data voltage having a low gray level is applied to the first subpixel electrode, and a data voltage having a high gray level is applied to the second subpixel electrode.