Advanced Dynamic Disk Memory Module

Abstract

Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory.

1 . A memory module; comprising:
 a first memory comprising a volatile memory;   a second memory comprising two or more non-volatile memory devices; and   a controller coupled to the first memory and the second memory, the controller comprising:
 a command interpreter; 
 one or more bus interface controller blocks coupled to the command 
   interpreter, each of the one or more bus interface controller blocks further coupled to a corresponding one of one or more bus interfaces;
 a first memory controller block, coupled to the command interpreter, for communicating with the first memory; and 
 a second memory controller block, coupled to the command interpreter, for communicating with the second memory, such that a first one of the two or more non-volatile memory devices is coupled to a first channel interface of the second memory controller block and a second one of the two or more non-volatile memory devices is coupled to a second channel interface of the second memory controller block; 
   at least one configuration register, the at least one configuration register coupled to the command interpreter;   wherein the memory module is adapted to physically and electrically couple to a computer system having a main memory, receive and store data from the computer system, and retrieve and transmit data to the computer system; wherein neither the first memory or the second memory form part of the main memory; wherein the command interpreter receives commands from the computer system; wherein the controller is operable to receive and store memory partition configuration information of the memory module; wherein the second memory controller block includes at least one alignment buffer to receive and store read data from each of the first and the second non-volatile memory devices, which read data arrives at the alignment buffer responsive to simultaneous read requests from the second memory controller block; and wherein the read data from each of the first and the second non-volatile memory devices arrives at a different time.   
   
   
       2 . The memory module of  claim 1 , wherein a first memory partition includes volatile memory only, a second memory partition includes volatile memory and non-volatile memory, and a third memory partition includes non-volatile memory only. 
   
   
       3 . The memory module of  claim 1 , further comprising a plurality of look-up tables coupled to the command interpreter. 
   
   
       4 . The memory module of  claim 1 , wherein data images are stored for accelerated access. 
   
   
       5 . The memory module of  claim 1 , wherein an OS boot image from a power-off or hibernate state is stored for use to improve system boot time from a power-off or hibernate state. 
   
   
       6 . The memory module of  claim 1 , wherein the volatile memory is a DRAM memory, and the non-volatile memory is a Flash memory. 
   
   
       7 . The memory module of  claim 1 , wherein the command interpreter is operable to receive an access request, determine the type of access, lookup first memory addresses and second memory addresses, send the access request to a first memory access queue if the first address is valid and the send the access request to a second memory access queue if the first address is not valid; and wherein the access request is selected from the group consisting of read access request and write access request. 
   
   
       8 . A memory module; comprising:
 a controller comprising:
 a command interpreter; 
 one or more bus interface controller blocks coupled to the command interpreter; 
 a first memory controller block, coupled to the command interpreter; 
 a second memory controller block, coupled to the command interpreter, the second memory controller block having a first channel interface, a second channel interface, and an alignment buffer coupled to each of the first and second channel interfaces; 
 at least one configuration register, the at least one configuration register coupled to the command interpreter; 
   a first memory comprising a volatile memory, the first memory coupled to the first memory controller block of the controller;   a second memory comprising two or more Flash memory devices, a first one of the two or more non-volatile memory devices coupled to the first channel interface, and a second one of the two or more non-volatile memory devices coupled to the second channel interface and   wherein the memory module is adapted to physically and electrically couple to a computer system having a main memory, receive and store data from the computer system, and retrieve and transmit data to the computer system; wherein the controller is operable to receive and store memory partition configuration information of the memory module; wherein the alignment buffer is operable to receive and store read data from each of the first and the second non-volatile memory devices, which read data arrives at the alignment buffer responsive to read requests from the first and second channel interfaces of the second memory controller block; and wherein the read data from each of the first and the second non-volatile memory devices arrives at a different time.   
   
   
       9 . The memory module of  claim 8 , wherein the volatile memory comprises DRAM and the non-volatile memory comprises Flash. 
   
   
       10 . A memory module; comprising:
 a controller comprising:
 a command interpreter; 
 one or more bus interface controller blocks coupled to the command interpreter; 
 a first memory controller block, coupled to the command interpreter; 
 a second memory controller block, coupled to the command interpreter, the second memory controller block having a first channel interface, a second channel interface, and an alignment buffer coupled to each of the first and second channel interfaces; 
 at least one configuration register, the at least one configuration register coupled to the command interpreter; 
   a second memory comprising two or more non-volatile memory devices, a first one of the two or more non-volatile memory devices coupled to the first channel interface, and a second one of the two or more non-volatile memory devices coupled to the second channel interface; and   wherein the memory module is adapted to physically and electrically couple to a computer system having a main memory, receive and store data from the computer system, and retrieve and transmit data to the computer system; wherein the controller is operable to receive and store memory partition configuration information of the memory module; wherein the controller is operable to determine whether a volatile memory is coupled to the first memory controller; wherein the alignment buffer is operable to receive and store read data from each of the first and the second non-volatile memory devices, which read data arrives at the alignment buffer responsive to parallel read requests from the first and second channel interfaces of the second memory controller block; and wherein the read data from each of the first and the second non-volatile memory devices arrives at a different time.   
   
   
       11 . The memory module of  claim 10 , further comprising a volatile memory, the volatile memory coupled to the first memory controller block. 
   
   
       12 . The memory module of  claim 11 , wherein the volatile memory comprises DRAM and the non-volatile memory comprises Flash. 
   
   
       13 . A memory module; comprising:
 a first memory comprising a volatile memory;   a second memory comprising two or more non-volatile memory devices; and   a controller coupled to the first memory and the second memory, the controller comprising:
 a command interpreter; 
 one or more bus interface controller blocks coupled to the command 
   interpreter, each of the one or more bus interface controller blocks further coupled to a corresponding one of one or more bus interfaces;
 a first memory controller block, coupled to the command interpreter, for communicating with the first memory; and 
 a second memory controller block, coupled to the command interpreter, for communicating with the second memory, such that a first one of the two or more non-volatile memory devices is coupled to a first channel interface of the second memory controller block and a second one of the two or more non-volatile memory devices is coupled to a second channel interface of the second memory controller block; 
   at least one configuration register, the at least one configuration register coupled to the command interpreter;   wherein the memory module is adapted to physically and electrically couple to a computer system having a main memory, receive and store data from the computer system, and retrieve and transmit data to the computer system; wherein neither the first memory or the second memory form part of the main memory; wherein the command interpreter receives commands from the computer system; wherein the controller is operable to receive and store memory partition configuration information of the memory module; wherein the second memory controller block includes at least one alignment buffer to receive and store read data from each of the first and the second non-volatile memory devices, which read data arrives at the alignment buffer responsive to parallel read requests from the second memory controller block; and wherein the read data from each of the first and the second non-volatile memory devices arrives at a different time.